MC100LVEP34 Clock Generation Chip

Welcome to the training module on the MC100LVEP34 Clock Generation Chip by On Semiconductor.
In this module, I will discuss the logic diagrams, timing digrams, clock distribution tree as well as some other key features.
The MC100LVEP34 is a low skew DIV2, DIV4 and DIV8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.
The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a run clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock; therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon start-up, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as multiple LVEP34s in a system. Single-ended CLK input operation is limited to a VCC ≥ 3.0 V in PECL mode, or VEE ≤ -3.0 V in NECL mode.
There are two distinct functional relationships between the Master Reset and Clock: The EN signal will “freeze” the internal divider flip-flops on the first falling edge of CLK after its assertion. The internal divider flip-flops will maintain their state during the freeze. When EN is de-asserted (LOW), and after the next falling edge of CLK, then the internal divider flip-flops will “unfreeze” and continue to their next state count with proper phase relationships
This is the continuation of the previous slide. In this slide, we show MR is de-asserted or high to low. After the Clock has transitioned low, the outputs will follow the third ensuing clock rising edge.
Here we show typical reset recovery graph of MC100LVEP34 device: case-1 refers to when MR occurs at high side of clock signal and case-2 refers to the situation when MR occurs at low side of clock signal.
This slide shows the curve for output voltage by Frequency. As you can see, when the device operates in divide by 2, the output voltage curve is constant at 700mV as long as the frequency is between 600-700Mhz. The output voltage curves slants downwards as frequency increases. When the device operates as a divide-by-4 or 8 the output voltage is constant at 700mV regardless of the frequency. This is a typical termination for this ECL output driver which is implemented between the driver device and the receiver device.
The skew introduced by logic devices can be divided into three parts: duty cycle skew, output-to-output skew and part-to-part skew. Depending on the specific application, each of the three components can be of equal or overriding importance. The duty cycle skew is a measure of the difference between the TPLH and TPHL propagation delays. Duty cycle skew is important in applications where timing operations occur on both edges or when the duty cycle of the clock signal is critical.
This slide addresses the output-output Skew: Output-to-output skew is defined as the difference between the propagation delays of all the outputs of a device. ECL devices provide superior performance in all three areas of skew over their TTL or CMOS competitors. A skew reducing mechanism common to all skew parameters is the faster propagation delays of ECL devices.
The Clock distribution in an ECL system is a relatively trivial matter, Here we show a two level clock distribution tree which produces nine differential ECL clocks on six different cards. The device also provides a multiplexed clock input for incorporating a high speed system clock and a lower speed test or scan clock within the same distribution tree. The ECL-in-PS-E1-11 device is used to receive the signals from the backplane and distribute it on the card. The worst case skew between all 54 clocks in this situation would be 275ps assuming that all the loads and signal traces are equalized.
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MC100LVEP34 Clock Generation Chip

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