Clock Generator/Jitter Cleaner with Integrated VCOs
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This training module provide a basic understanding of how clocks work and the various functions & key parameters of clocks, and introduces the CDCE62005 clock generator
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Clock Generator/Jitter Cleaner with Integrated VCOs
- 3. Clocks in the Signal Chain Power Management Signal Conditioning Temperature Pressure Position Speed Flow Humidity Sound Light The Real World Analog Signal Conversion to Digital Digital Signal Conversion to Analog Signal Conditioning Interface Clocks DSP/FPGA/ASIC
- 7. Jitter Cleaner Jitter Cleaner: Any PLL-based clock that cleans the noises from the reference clock and provides a clean and synchronized signal for the receivers using an external VCO (VCXO) or internal VCO. Ideal Input clock: Real Input clock with Jitter: Jitter Cleaning using a VCXO VCXO Ideal Input clock: Clean Clock: LPF CDC V304
- 10. Propagation Delay Propagation delay time, t pd : The time between the specified reference points on the input and output voltage waveforms with the output changing from one defined level (High or Low) to the other defined level. It is common to have a propagation delay of ~3 ns. t pd = t PHL or t PLH
- 11. Output Skew Output Skew, t sk(o) : The difference between any two propagation delay times when input switching causes multiple outputs switching. Common output skew can range anywhere from 100 ps to 500 ps.
- 14. Block Diagram
- 16. CDCE62005 Interface to ADC Figure 1 Figure 2
Notas do Editor
- This is a training module for the Texas Instruments Clock Generator / Jitter Cleaner with Integrated VCOs
- Welcome to the training module on the Texas Instruments Clock Generator/Jitter Cleaner with Integrated VCOs. This training module provides a basic understanding of how clocks work, the various functions that they can provide within a system, and the key parameters of clocking devices. It will also introduce the CDCE62005 clock generator and jitter cleaner.
- This graphical representation of the signal chain is intended to show the major blocks within an electric system and to highlight where clocks fit into this system. As shown, the clock interacts with all of the digital blocks in the design including the processing unit, data converters, and interface components.
- At the most basic level, a clock is a device that generates periodic signals at a specific frequency. Systems that need a reference to time for synchronization, command execution, or data transfer will use this periodic signal to perform these functions. Typical devices within the signal chain that perform these functions are those that interact with digital signals such as the processing unit, which can be either a DSP, FPGA, or ASIC, the data converters, and interface components such as USB or SERDES. The network of clocking devices provides the frequencies to each of the system blocks so that it can perform its intended function.
- A basic clock circuit works by receiving an input frequency from a source and either distributing that frequency or generating new frequencies to send as outputs to other devices within the system. This can either be done using Phases Locked Loop (PLL) or non-PLL based circuitry. The input to the clock can come from either a crystal or from another device within the system. A system signal is either single-ended or differential, which is defined by the source device. The main difference between PLL and non-PLL clocks is that the PLL uses a feedback loop to remove the time delay between the signal input and output, known as propagation delay. The feedback loop also allows the PLL to act as a phase detector to keep an oscillator in phase with an incoming frequency. PLL clocks are able to eliminate propagation delay, move the output phase with respect to the input phase, make duty cycle corrections, perform integer or fractional multiplication, and remove noise from the reference clock. PLL clocks are used when the system needs to minimize the propagation delay.
- There are two main functions that a clocking device can perform, either signal distribution or generation. Fanout buffers are solely used for distribution, while Multipliers/Dividers and Synthesizers are used for both distribution and generation. A Jitter Cleaner can be any of the clocking devices listed.
- One type of clock that is commonly found in highly sensitive electronic systems is known as a jitter cleaner. Jitter is a term used to represent the various types of noise associated with a clock signal. A jitter cleaner is any PLL based clocking device that removes this noise from the reference signal and provides a clean and synchronous output signal. Jitter is usually removed from the reference clock by setting the loop of the PLL to a low bandwidth.
- It is important to note that a specific system will require a unique combination of the parameters listed here. The first characteristic to determine the appropriate clocking solution will be the signaling level that the system requires. A signaling level is either single-ended or differential. The common types of single-ended signals are LVCMOS, TTL, and LVTTL and they support up to roughly 250 MHz. The common types of differential signals are LVDS, LVPECL, CML PCI Express, SSTL, HSTL and they can support up to 10+ GHz. The signaling level will be defined by the type of system and application needing the clock. For example, if you are choosing a clocking device to support a communications basestation you would be using a differential signal that supports higher frequencies such as LVDS or LVPECL. The second characteristic used to determine the appropriate solution is the required system performance. Common performance metrics are Jitter, Propagation Delay, and Output Skew. We will go into more detail on each of these in the following slides. Other factors to consider in selecting a clocking solution will be number of outputs needed, number of frequencies, the input voltage and frequency, and the required output frequencies.
- Jitter is the most commonly used measurement of clock performance and it is defined as any deviation of the actual signal edge from the ideal edge. The three most common types of jitter are period, cycle to cycle, and phase jitter. Common Jitter performance can range from < 200 fs to 100 ps. Period jitter is the difference between the actual cycle time and the ideal period defined as 1/f. This is also referred to as short term jitter. Cycle to Cycle Jitter is the variation in the cycle time between consecutive cycles over a random sample of cycle pairs. It is also referred to as adjacent cycle jitter. Phase Jitter, also known as long term jitter, is the integration of the phase noise plot in time over a specified band of frequencies.
- Propagation delay is the time difference between a reference point on the input signal and the same point on the output signal, specifically when the output changes from one defined level, either high or low, to the other.
- Output skew is the difference between the propagation delay of each of the outputs. For example, in a fanout buffer with a single input and two identical outputs, the output skew would be the difference between the propagation delay of each output.
- The CDCE62005 is a low phase noise, low jitter clock synthesizer and jitter cleaner with programmable outputs and inputs. It features a phase-locked loop (PLL) architecture with an on-chip voltage-controlled oscillator (VCO) and internal loop filter. An optional external low-pass loop filter is required to complete the PLL. The CDCE62005 features a high degree of configurability via a SPI interface, and programmable startup modes determined by integrated EEPROM. Specifically tailored for clocking data converters and high-speed digital signals, the CDCE62005 achieves jitter performance well under 1-ps RMS. It incorporates a synthesizer block with partially integrated loop filter, a clock distribution block including programmable output formats, and an input block featuring an innovative smart multiplexer.
- The typical applications for this clocking devices are communications, consumer products, medical electronics, military and aerospace, and industrial applications. For communication designs, the most important parameter considerations are high performance requirements such as very low jitter as well as differential inputs to support higher speeds. For consumer applications it is common to find designs requiring high frequency accuracy and requiring multiple frequencies.
- The CDCE62005 comprises of four primary blocks: the interface and control block, the input block, the output block, and the synthesizer block. The interface and control block determines the state of the CDCE62005 at power-up based on the contents of the on-board EEPROM. In addition to the EEPROM, the SPI port is available to configure the CDCE62005 by writing directly to the device registers after power-up. The input block selects which of the three input ports is available for use by the synthesizer block and buffers all clock inputs. The output block provides five separate clock channels that are fully programmable and configurable to select and condition one of four internal clock sources. The synthesizer block multiplies and filters the input clock selected by the input block.
- The clock distribution block includes five individually programmable outputs that can be configured to provide different combinations of output formats. Each output can also be programmed to a unique output frequency and skew relationship via a programmable delay block. If all outputs are configured in single-ended mode, the CDCE62005 supports up to ten outputs. In the example as shown, the CDCE62005 provides 4 clock sources for DSP, 2 ADCs and 1 ADC.
- In order to realize the full potential of high IF, high sampling rate ADCs, it is important that the clock source have low phase noise. With proper configuration, the CDCE62005 can be used with high-speed ADCs to achieve ideal performance suitable for direct implementation into printed circuit board (PCB) designs. For low IF input frequencies to an ADC, the CDCE62005 output can be configured as a high swing LVPECL signal and interfaced to the ADC as shown in Figure 1. Using the differential output is ideal in this case, because it minimizes the susceptibility of outside noise coupling on the line. For medium to high IF input frequencies to the ADC, the CDCE62005 output can be configured as an LVCMOS signal and interfaced to the ADC as shown in Figure 2. In this case, the crystal filter is used to remove excessive noise from the clock signal.
- Here shows a solution on how to generate networking LAN clocks from a single CDCE62005 device. For LAN applications, typical clock speeds are 625 MHz, 312.5 MHz, 156.25 MHz, 125 MHz, and 25 MHz and the output signal type needed can be differential (LVPECL or LVDS) or single ended 3.3V LVCMOS. The 25 MHz is then fed into the CDCE62005 VCO core to generate a 625 MHz frequency available to all five output muxes.
- Here is an example on how to generate networking WAN clocks from a single CDCE62005 device. For WAN applications, the clock speeds are 622.08 MHz, 311.04 MHz, 155.52 MHz, 77.76 MHz, and 19.44 MHz are commonly used. Similar to LAN systems, WAN systems need the differential (LVPECL or LVDS) or single ended 3.3V LVCMOS output of the CDCE62005. In this case, a 24.8832 MHz is feed into the CDCE62005 VCO core to generate a 622.08 MHz frequency available to all five output muxes.
- Thank you for taking the time to view this presentation on “ Clock Generator/Jitter Cleaner with Integrated VCOs” . If you would like to learn more or go on to purchase some of these devices, you may either click on the part list link, or simply call our sales hotline. For more technical information you may either visit the Texas Instruments site, if you would prefer to speak to someone live, please call our hotline number, or even use our ‘live chat’ online facility.