SlideShare a Scribd company logo

Chapter 5 a

•
•
E
ececourse
EducationTechnology
1 of 31
Chapter 5 Large and Fast: Exploiting Memory Hierarchy
Memory Technology ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — §5.1 Introduction
Principle of Locality ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Chapter 5 — Large and Fast: Exploiting Memory Hierarchy —
Taking Advantage of Locality ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Chapter 5 — Large and Fast: Exploiting Memory Hierarchy —
Memory Hierarchy Levels ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Chapter 5 — Large and Fast: Exploiting Memory Hierarchy —
Cache Memory ,[object Object],[object Object],[object Object],Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — §5.2 The Basics of Caches ,[object Object],[object Object]
Direct Mapped Cache ,[object Object],[object Object],[object Object],Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — ,[object Object],[object Object]
Tags and Valid Bits ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Chapter 5 — Large and Fast: Exploiting Memory Hierarchy —
Cache Example ,[object Object],[object Object],Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — Index V Tag Data 000 N 001 N 010 N 011 N 100 N 101 N 110 N 111 N
Cache Example Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — Index V Tag Data 000 N 001 N 010 N 011 N 100 N 101 N 110 Y 10 Mem[10110] 111 N Word addr Binary addr Hit/miss Cache block 22 10 110 Miss 110
Cache Example Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — Index V Tag Data 000 N 001 N 010 Y 11 Mem[11010] 011 N 100 N 101 N 110 Y 10 Mem[10110] 111 N Word addr Binary addr Hit/miss Cache block 26 11 010 Miss 010
Cache Example Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — Index V Tag Data 000 N 001 N 010 Y 11 Mem[11010] 011 N 100 N 101 N 110 Y 10 Mem[10110] 111 N Word addr Binary addr Hit/miss Cache block 22 10 110 Hit 110 26 11 010 Hit 010
Cache Example Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — Index V Tag Data 000 Y 10 Mem[10000] 001 N 010 Y 11 Mem[11010] 011 Y 00 Mem[00011] 100 N 101 N 110 Y 10 Mem[10110] 111 N Word addr Binary addr Hit/miss Cache block 16 10 000 Miss 000 3 00 011 Miss 011 16 10 000 Hit 000
Cache Example Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — Index V Tag Data 000 Y 10 Mem[10000] 001 N 010 Y 10 Mem[10010] 011 Y 00 Mem[00011] 100 N 101 N 110 Y 10 Mem[10110] 111 N Word addr Binary addr Hit/miss Cache block 18 10 010 Miss 010
Address Subdivision Chapter 5 — Large and Fast: Exploiting Memory Hierarchy —
Example: Larger Block Size ,[object Object],[object Object],[object Object],[object Object],Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — Tag Index Offset 0 3 4 9 10 31 4 bits 6 bits 22 bits
Block Size Considerations ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Chapter 5 — Large and Fast: Exploiting Memory Hierarchy —
Cache Misses ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Chapter 5 — Large and Fast: Exploiting Memory Hierarchy —
Write-Through ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Chapter 5 — Large and Fast: Exploiting Memory Hierarchy —
Write-Back ,[object Object],[object Object],[object Object],[object Object],[object Object],Chapter 5 — Large and Fast: Exploiting Memory Hierarchy —
Write Allocation ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Chapter 5 — Large and Fast: Exploiting Memory Hierarchy —
Example: Intrinsity FastMATH ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Chapter 5 — Large and Fast: Exploiting Memory Hierarchy —
Example: Intrinsity FastMATH Chapter 5 — Large and Fast: Exploiting Memory Hierarchy —
Main Memory Supporting Caches ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Chapter 5 — Large and Fast: Exploiting Memory Hierarchy —
Increasing Memory Bandwidth Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Advanced DRAM Organization ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Chapter 5 — Large and Fast: Exploiting Memory Hierarchy —
DRAM Generations Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — Year Capacity $/GB 1980 64Kbit $1500000 1983 256Kbit $500000 1985 1Mbit $200000 1989 4Mbit $50000 1992 16Mbit $15000 1996 64Mbit $10000 1998 128Mbit $4000 2000 256Mbit $1000 2004 512Mbit $250 2007 1Gbit $50
Measuring Cache Performance ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — §5.3 Measuring and Improving Cache Performance
Cache Performance Example ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Chapter 5 — Large and Fast: Exploiting Memory Hierarchy —
Average Access Time ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Chapter 5 — Large and Fast: Exploiting Memory Hierarchy —
Performance Summary ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Chapter 5 — Large and Fast: Exploiting Memory Hierarchy —

Recommended

Chapter 5 c
Chapter 5 cChapter 5 c
Chapter 5 cececourse
 
Chapter 5 b
Chapter 5 bChapter 5 b
Chapter 5 bececourse
 
Chapter 4 The Processor
Chapter 4 The ProcessorChapter 4 The Processor
Chapter 4 The Processorguest4f73554
 
Chapter 4
Chapter 4Chapter 4
Chapter 4ececourse
 
Chapter 3
Chapter 3Chapter 3
Chapter 3ececourse
 
Cache Memory
Cache Memory Cache Memory
Cache Memory sathish sak
 
Instruction Level Parallelism and Superscalar Processors
Instruction Level Parallelism and Superscalar ProcessorsInstruction Level Parallelism and Superscalar Processors
Instruction Level Parallelism and Superscalar ProcessorsSyed Zaid Irshad
 
Nehalem (microarchitecture)
Nehalem (microarchitecture)Nehalem (microarchitecture)
Nehalem (microarchitecture)Amirali Sharifian
 

Recommended

Chapter 5 c
Chapter 5 cChapter 5 c
Chapter 5 cececourse
 
Chapter 5 b
Chapter 5 bChapter 5 b
Chapter 5 bececourse
 
Chapter 4 The Processor
Chapter 4 The ProcessorChapter 4 The Processor
Chapter 4 The Processorguest4f73554
 
Chapter 4
Chapter 4Chapter 4
Chapter 4ececourse
 
Chapter 3
Chapter 3Chapter 3
Chapter 3ececourse
 
Cache Memory
Cache Memory Cache Memory
Cache Memory sathish sak
 
Instruction Level Parallelism and Superscalar Processors
Instruction Level Parallelism and Superscalar ProcessorsInstruction Level Parallelism and Superscalar Processors
Instruction Level Parallelism and Superscalar ProcessorsSyed Zaid Irshad
 
Nehalem (microarchitecture)
Nehalem (microarchitecture)Nehalem (microarchitecture)
Nehalem (microarchitecture)Amirali Sharifian
 
Unit iii
Unit iiiUnit iii
Unit iiiJanani S
 
Instruction Set Architecture – II
Instruction Set Architecture – IIInstruction Set Architecture – II
Instruction Set Architecture – IIDilum Bandara
 
Chapter 4 the processor
Chapter 4 the processorChapter 4 the processor
Chapter 4 the processors9007912
 
Unit 5 Advanced Computer Architecture
Unit 5 Advanced Computer ArchitectureUnit 5 Advanced Computer Architecture
Unit 5 Advanced Computer ArchitectureBalaji Vignesh
 
Unit IV Memory and I/O Organization
Unit IV Memory and I/O OrganizationUnit IV Memory and I/O Organization
Unit IV Memory and I/O OrganizationBalaji Vignesh
 
Micro programmed control
Micro programmed controlMicro programmed control
Micro programmed controlShashank Singh
 
Datapath Design of Computer Architecture
Datapath Design of Computer ArchitectureDatapath Design of Computer Architecture
Datapath Design of Computer ArchitectureAbu Zaman
 
Lecture6 memory hierarchy
Lecture6 memory hierarchyLecture6 memory hierarchy
Lecture6 memory hierarchyli12x
 
Cache coherence
Cache coherenceCache coherence
Cache coherencePriyam Pandey
 
Multithreaded processors ppt
Multithreaded processors pptMultithreaded processors ppt
Multithreaded processors pptSiddhartha Anand
 
Memory organization
Memory organizationMemory organization
Memory organizationDhaval Bagal
 
Multicore Computers
Multicore ComputersMulticore Computers
Multicore ComputersA B Shinde
 
Intel Pentium Pro
Intel Pentium ProIntel Pentium Pro
Intel Pentium ProMuhtasim Fuad Rafid
 
Intel’s core i7
Intel’s core i7Intel’s core i7
Intel’s core i7Chandresh Mahajan
 
Lecture 3 instruction set
Lecture 3 instruction setLecture 3 instruction set
Lecture 3 instruction setPradeep Kumar TS
 
Cache Memory
Cache MemoryCache Memory
Cache MemorySubid Biswas
 
Control Unit Design
Control Unit DesignControl Unit Design
Control Unit DesignVinit Raut
 
Computer architecture instruction formats
Computer architecture instruction formatsComputer architecture instruction formats
Computer architecture instruction formatsMazin Alwaaly
 
Write miss
Write missWrite miss
Write missmarangburu42
 
What is Cache and how it works
What is Cache and how it worksWhat is Cache and how it works
What is Cache and how it worksTabraiz Yaseen
 
Chapter 1 computer abstractions and technology
Chapter 1 computer abstractions and technologyChapter 1 computer abstractions and technology
Chapter 1 computer abstractions and technologyBATMUNHMUNHZAYA
 
Chapter 2 instructions language of the computer
Chapter 2 instructions language of the computerChapter 2 instructions language of the computer
Chapter 2 instructions language of the computerBATMUNHMUNHZAYA
 

More Related Content

What's hot

Instruction Set Architecture – II
Instruction Set Architecture – IIInstruction Set Architecture – II
Instruction Set Architecture – IIDilum Bandara
 
Chapter 4 the processor
Chapter 4 the processorChapter 4 the processor
Chapter 4 the processors9007912
 
Unit 5 Advanced Computer Architecture
Unit 5 Advanced Computer ArchitectureUnit 5 Advanced Computer Architecture
Unit 5 Advanced Computer ArchitectureBalaji Vignesh
 
Unit IV Memory and I/O Organization
Unit IV Memory and I/O OrganizationUnit IV Memory and I/O Organization
Unit IV Memory and I/O OrganizationBalaji Vignesh
 
Micro programmed control
Micro programmed controlMicro programmed control
Micro programmed controlShashank Singh
 
Datapath Design of Computer Architecture
Datapath Design of Computer ArchitectureDatapath Design of Computer Architecture
Datapath Design of Computer ArchitectureAbu Zaman
 
Lecture6 memory hierarchy
Lecture6 memory hierarchyLecture6 memory hierarchy
Lecture6 memory hierarchyli12x
 
Multithreaded processors ppt
Multithreaded processors pptMultithreaded processors ppt
Multithreaded processors pptSiddhartha Anand
 
Memory organization
Memory organizationMemory organization
Memory organizationDhaval Bagal
 
Multicore Computers
Multicore ComputersMulticore Computers
Multicore ComputersA B Shinde
 
Control Unit Design
Control Unit DesignControl Unit Design
Control Unit DesignVinit Raut
 
Computer architecture instruction formats
Computer architecture instruction formatsComputer architecture instruction formats
Computer architecture instruction formatsMazin Alwaaly
 
What is Cache and how it works
What is Cache and how it worksWhat is Cache and how it works
What is Cache and how it worksTabraiz Yaseen
 

What's hot (20)

Unit iii
Unit iiiUnit iii
Unit iii
 
Instruction Set Architecture – II
Instruction Set Architecture – IIInstruction Set Architecture – II
Instruction Set Architecture – II
 
Chapter 4 the processor
Chapter 4 the processorChapter 4 the processor
Chapter 4 the processor
 
Unit 5 Advanced Computer Architecture
Unit 5 Advanced Computer ArchitectureUnit 5 Advanced Computer Architecture
Unit 5 Advanced Computer Architecture
 
Unit IV Memory and I/O Organization
Unit IV Memory and I/O OrganizationUnit IV Memory and I/O Organization
Unit IV Memory and I/O Organization
 
Micro programmed control
Micro programmed controlMicro programmed control
Micro programmed control
 
Datapath Design of Computer Architecture
Datapath Design of Computer ArchitectureDatapath Design of Computer Architecture
Datapath Design of Computer Architecture
 
Lecture6 memory hierarchy
Lecture6 memory hierarchyLecture6 memory hierarchy
Lecture6 memory hierarchy
 
Cache coherence
Cache coherenceCache coherence
Cache coherence
 
Multithreaded processors ppt
Multithreaded processors pptMultithreaded processors ppt
Multithreaded processors ppt
 
Memory organization
Memory organizationMemory organization
Memory organization
 
Multicore Computers
Multicore ComputersMulticore Computers
Multicore Computers
 
Intel Pentium Pro
Intel Pentium ProIntel Pentium Pro
Intel Pentium Pro
 
Intel’s core i7
Intel’s core i7Intel’s core i7
Intel’s core i7
 
Lecture 3 instruction set
Lecture 3 instruction setLecture 3 instruction set
Lecture 3 instruction set
 
Cache Memory
Cache MemoryCache Memory
Cache Memory
 
Control Unit Design
Control Unit DesignControl Unit Design
Control Unit Design
 
Computer architecture instruction formats
Computer architecture instruction formatsComputer architecture instruction formats
Computer architecture instruction formats
 
Write miss
Write missWrite miss
Write miss
 
What is Cache and how it works
What is Cache and how it worksWhat is Cache and how it works
What is Cache and how it works
 

Viewers also liked

Chapter 1 computer abstractions and technology
Chapter 1 computer abstractions and technologyChapter 1 computer abstractions and technology
Chapter 1 computer abstractions and technologyBATMUNHMUNHZAYA
 
Chapter 2 instructions language of the computer
Chapter 2 instructions language of the computerChapter 2 instructions language of the computer
Chapter 2 instructions language of the computerBATMUNHMUNHZAYA
 
Chapter 2 Hw
Chapter 2 HwChapter 2 Hw
Chapter 2 Hwececourse
 
C:\Fakepath\Chapter 2 Part2 B
C:\Fakepath\Chapter 2 Part2 BC:\Fakepath\Chapter 2 Part2 B
C:\Fakepath\Chapter 2 Part2 Bececourse
 
Chapter 2 Part2 C
Chapter 2 Part2 CChapter 2 Part2 C
Chapter 2 Part2 Cececourse
 
Chapter 2 Part2 A
Chapter 2 Part2 AChapter 2 Part2 A
Chapter 2 Part2 Aececourse
 
VTU 4TH SEM CSE COMPUTER ORGANIZATION SOLVED PAPERS OF JUNE-2013 JUNE-2014 & ...
VTU 4TH SEM CSE COMPUTER ORGANIZATION SOLVED PAPERS OF JUNE-2013 JUNE-2014 & ...VTU 4TH SEM CSE COMPUTER ORGANIZATION SOLVED PAPERS OF JUNE-2013 JUNE-2014 & ...
VTU 4TH SEM CSE COMPUTER ORGANIZATION SOLVED PAPERS OF JUNE-2013 JUNE-2014 & ...vtunotesbysree
 

Viewers also liked (7)

Chapter 1 computer abstractions and technology
Chapter 1 computer abstractions and technologyChapter 1 computer abstractions and technology
Chapter 1 computer abstractions and technology
 
Chapter 2 instructions language of the computer
Chapter 2 instructions language of the computerChapter 2 instructions language of the computer
Chapter 2 instructions language of the computer
 
Chapter 2 Hw
Chapter 2 HwChapter 2 Hw
Chapter 2 Hw
 
C:\Fakepath\Chapter 2 Part2 B
C:\Fakepath\Chapter 2 Part2 BC:\Fakepath\Chapter 2 Part2 B
C:\Fakepath\Chapter 2 Part2 B
 
Chapter 2 Part2 C
Chapter 2 Part2 CChapter 2 Part2 C
Chapter 2 Part2 C
 
Chapter 2 Part2 A
Chapter 2 Part2 AChapter 2 Part2 A
Chapter 2 Part2 A
 
VTU 4TH SEM CSE COMPUTER ORGANIZATION SOLVED PAPERS OF JUNE-2013 JUNE-2014 & ...
VTU 4TH SEM CSE COMPUTER ORGANIZATION SOLVED PAPERS OF JUNE-2013 JUNE-2014 & ...VTU 4TH SEM CSE COMPUTER ORGANIZATION SOLVED PAPERS OF JUNE-2013 JUNE-2014 & ...
VTU 4TH SEM CSE COMPUTER ORGANIZATION SOLVED PAPERS OF JUNE-2013 JUNE-2014 & ...
 

Similar to Chapter 5 a

CPU Memory Hierarchy and Caching Techniques
CPU Memory Hierarchy and Caching TechniquesCPU Memory Hierarchy and Caching Techniques
CPU Memory Hierarchy and Caching TechniquesDilum Bandara
 
Memory Hierarchy Design, Basics, Cache Optimization, Address Translation
Memory Hierarchy Design, Basics, Cache Optimization, Address TranslationMemory Hierarchy Design, Basics, Cache Optimization, Address Translation
Memory Hierarchy Design, Basics, Cache Optimization, Address TranslationFarwa Ansari
 
Cpu caching concepts mr mahesh
Cpu caching concepts mr maheshCpu caching concepts mr mahesh
Cpu caching concepts mr maheshFaridabad
 
hierarchical memory technology.pptx
hierarchical memory technology.pptxhierarchical memory technology.pptx
hierarchical memory technology.pptx2105986
 
CPU Caching Concepts
CPU Caching ConceptsCPU Caching Concepts
CPU Caching ConceptsAbhijit K Rao
 
Memory Hierarchy PPT of Computer Organization
Memory Hierarchy PPT of Computer OrganizationMemory Hierarchy PPT of Computer Organization
Memory Hierarchy PPT of Computer Organization2022002857mbit
 
Computer Memory Hierarchy Computer Architecture
Computer Memory Hierarchy Computer ArchitectureComputer Memory Hierarchy Computer Architecture
Computer Memory Hierarchy Computer ArchitectureHaris456
 
amer-memory1.ppt
amer-memory1.pptamer-memory1.ppt
amer-memory1.pptRohitPaul71
 
Ways to reduce misses
Ways to reduce missesWays to reduce misses
Ways to reduce missesnellins
 
onur-comparch-fall2018-lecture3b-memoryhierarchyandcaches-afterlecture.pptx
onur-comparch-fall2018-lecture3b-memoryhierarchyandcaches-afterlecture.pptxonur-comparch-fall2018-lecture3b-memoryhierarchyandcaches-afterlecture.pptx
onur-comparch-fall2018-lecture3b-memoryhierarchyandcaches-afterlecture.pptxsivasubramanianManic2
 
Unit I Memory technology and optimization
Unit I Memory technology and optimizationUnit I Memory technology and optimization
Unit I Memory technology and optimizationK Gowsic Gowsic
 
Memory technology and optimization in Advance Computer Architechture
Memory technology and optimization in Advance Computer ArchitechtureMemory technology and optimization in Advance Computer Architechture
Memory technology and optimization in Advance Computer ArchitechtureShweta Ghate
 
cache cache memory memory cache memory.pptx
cache cache memory memory cache memory.pptxcache cache memory memory cache memory.pptx
cache cache memory memory cache memory.pptxsaimawarsi
 
High Performance Computer Architecture
High Performance Computer ArchitectureHigh Performance Computer Architecture
High Performance Computer ArchitectureSubhasis Dash
 

Similar to Chapter 5 a (20)

CPU Memory Hierarchy and Caching Techniques
CPU Memory Hierarchy and Caching TechniquesCPU Memory Hierarchy and Caching Techniques
CPU Memory Hierarchy and Caching Techniques
 
Memory Hierarchy Design, Basics, Cache Optimization, Address Translation
Memory Hierarchy Design, Basics, Cache Optimization, Address TranslationMemory Hierarchy Design, Basics, Cache Optimization, Address Translation
Memory Hierarchy Design, Basics, Cache Optimization, Address Translation
 
computer-memory
computer-memorycomputer-memory
computer-memory
 
Memory Organization
Memory OrganizationMemory Organization
Memory Organization
 
Cpu caching concepts mr mahesh
Cpu caching concepts mr maheshCpu caching concepts mr mahesh
Cpu caching concepts mr mahesh
 
hierarchical memory technology.pptx
hierarchical memory technology.pptxhierarchical memory technology.pptx
hierarchical memory technology.pptx
 
CPU Caching Concepts
CPU Caching ConceptsCPU Caching Concepts
CPU Caching Concepts
 
Memory Hierarchy PPT of Computer Organization
Memory Hierarchy PPT of Computer OrganizationMemory Hierarchy PPT of Computer Organization
Memory Hierarchy PPT of Computer Organization
 
Computer Memory Hierarchy Computer Architecture
Computer Memory Hierarchy Computer ArchitectureComputer Memory Hierarchy Computer Architecture
Computer Memory Hierarchy Computer Architecture
 
amer-memory1.ppt
amer-memory1.pptamer-memory1.ppt
amer-memory1.ppt
 
Memory Management
Memory ManagementMemory Management
Memory Management
 
1083 wang
1083 wang1083 wang
1083 wang
 
Cache optimization
Cache optimizationCache optimization
Cache optimization
 
Ways to reduce misses
Ways to reduce missesWays to reduce misses
Ways to reduce misses
 
Cache memory
Cache memoryCache memory
Cache memory
 
onur-comparch-fall2018-lecture3b-memoryhierarchyandcaches-afterlecture.pptx
onur-comparch-fall2018-lecture3b-memoryhierarchyandcaches-afterlecture.pptxonur-comparch-fall2018-lecture3b-memoryhierarchyandcaches-afterlecture.pptx
onur-comparch-fall2018-lecture3b-memoryhierarchyandcaches-afterlecture.pptx
 
Unit I Memory technology and optimization
Unit I Memory technology and optimizationUnit I Memory technology and optimization
Unit I Memory technology and optimization
 
Memory technology and optimization in Advance Computer Architechture
Memory technology and optimization in Advance Computer ArchitechtureMemory technology and optimization in Advance Computer Architechture
Memory technology and optimization in Advance Computer Architechture
 
cache cache memory memory cache memory.pptx
cache cache memory memory cache memory.pptxcache cache memory memory cache memory.pptx
cache cache memory memory cache memory.pptx
 
High Performance Computer Architecture
High Performance Computer ArchitectureHigh Performance Computer Architecture
High Performance Computer Architecture
 

More from ececourse

Machine Problem 2
Machine Problem 2Machine Problem 2
Machine Problem 2ececourse
 
Machine Problem 1
Machine Problem 1Machine Problem 1
Machine Problem 1ececourse
 
Chapter 2 Part1
Chapter 2 Part1Chapter 2 Part1
Chapter 2 Part1ececourse
 

More from ececourse (6)

Auxiliary
AuxiliaryAuxiliary
Auxiliary
 
Mem Tb
Mem TbMem Tb
Mem Tb
 
Machine Problem 2
Machine Problem 2Machine Problem 2
Machine Problem 2
 
Machine Problem 1
Machine Problem 1Machine Problem 1
Machine Problem 1
 
Chapter1
Chapter1Chapter1
Chapter1
 
Chapter 2 Part1
Chapter 2 Part1Chapter 2 Part1
Chapter 2 Part1
 

Recently uploaded

Software Engineering Methodologies (overview)
Software Engineering Methodologies (overview)Software Engineering Methodologies (overview)
Software Engineering Methodologies (overview)eniolaolutunde
 
BASLIQ CURRENT LOOKBOOK LOOKBOOK(1) (1).pdf
BASLIQ CURRENT LOOKBOOK LOOKBOOK(1) (1).pdfBASLIQ CURRENT LOOKBOOK LOOKBOOK(1) (1).pdf
BASLIQ CURRENT LOOKBOOK LOOKBOOK(1) (1).pdfSoniaTolstoy
 
The basics of sentences session 2pptx copy.pptx
The basics of sentences session 2pptx copy.pptxThe basics of sentences session 2pptx copy.pptx
The basics of sentences session 2pptx copy.pptxheathfieldcps1
 
Introduction to Nonprofit Accounting: The Basics
Introduction to Nonprofit Accounting: The BasicsIntroduction to Nonprofit Accounting: The Basics
Introduction to Nonprofit Accounting: The BasicsTechSoup
 
Advanced Views - Calendar View in Odoo 17
Advanced Views - Calendar View in Odoo 17Advanced Views - Calendar View in Odoo 17
Advanced Views - Calendar View in Odoo 17Celine George
 
Unit-IV- Pharma. Marketing Channels.pptx
Unit-IV- Pharma. Marketing Channels.pptxUnit-IV- Pharma. Marketing Channels.pptx
Unit-IV- Pharma. Marketing Channels.pptxVishalSingh1417
 
Interactive Powerpoint_How to Master effective communication
Interactive Powerpoint_How to Master effective communicationInteractive Powerpoint_How to Master effective communication
Interactive Powerpoint_How to Master effective communicationnomboosow
 
Call Girls in Dwarka Mor Delhi Contact Us 9654467111
Call Girls in Dwarka Mor Delhi Contact Us 9654467111Call Girls in Dwarka Mor Delhi Contact Us 9654467111
Call Girls in Dwarka Mor Delhi Contact Us 9654467111Sapana Sha
 
fourth grading exam for kindergarten in writing
fourth grading exam for kindergarten in writingfourth grading exam for kindergarten in writing
fourth grading exam for kindergarten in writingTeacherCyreneCayanan
 
General AI for Medical Educators April 2024
General AI for Medical Educators April 2024General AI for Medical Educators April 2024
General AI for Medical Educators April 2024Janet Corral
 
Sports & Fitness Value Added Course FY..
Sports & Fitness Value Added Course FY..Sports & Fitness Value Added Course FY..
Sports & Fitness Value Added Course FY..Disha Kariya
 
Accessible design: Minimum effort, maximum impact
Accessible design: Minimum effort, maximum impactAccessible design: Minimum effort, maximum impact
Accessible design: Minimum effort, maximum impactdawncurless
 
APM Welcome, APM North West Network Conference, Synergies Across Sectors
APM Welcome, APM North West Network Conference, Synergies Across SectorsAPM Welcome, APM North West Network Conference, Synergies Across Sectors
APM Welcome, APM North West Network Conference, Synergies Across SectorsAssociation for Project Management
 
1029-Danh muc Sach Giao Khoa khoi 6.pdf
1029-Danh muc Sach Giao Khoa khoi 6.pdf1029-Danh muc Sach Giao Khoa khoi 6.pdf
1029-Danh muc Sach Giao Khoa khoi 6.pdfQucHHunhnh
 
A Critique of the Proposed National Education Policy Reform
A Critique of the Proposed National Education Policy ReformA Critique of the Proposed National Education Policy Reform
A Critique of the Proposed National Education Policy ReformChameera Dedduwage
 
BAG TECHNIQUE Bag technique-a tool making use of public health bag through wh...
BAG TECHNIQUE Bag technique-a tool making use of public health bag through wh...BAG TECHNIQUE Bag technique-a tool making use of public health bag through wh...
BAG TECHNIQUE Bag technique-a tool making use of public health bag through wh...Sapna Thakur
 
Disha NEET Physics Guide for classes 11 and 12.pdf
Disha NEET Physics Guide for classes 11 and 12.pdfDisha NEET Physics Guide for classes 11 and 12.pdf
Disha NEET Physics Guide for classes 11 and 12.pdfchloefrazer622
 
Key note speaker Neum_Admir Softic_ENG.pdf
Key note speaker Neum_Admir Softic_ENG.pdfKey note speaker Neum_Admir Softic_ENG.pdf
Key note speaker Neum_Admir Softic_ENG.pdfAdmir Softic
 

Recently uploaded (20)

Software Engineering Methodologies (overview)
Software Engineering Methodologies (overview)Software Engineering Methodologies (overview)
Software Engineering Methodologies (overview)
 
Mattingly "AI & Prompt Design: The Basics of Prompt Design"
Mattingly "AI & Prompt Design: The Basics of Prompt Design"Mattingly "AI & Prompt Design: The Basics of Prompt Design"
Mattingly "AI & Prompt Design: The Basics of Prompt Design"
 
BASLIQ CURRENT LOOKBOOK LOOKBOOK(1) (1).pdf
BASLIQ CURRENT LOOKBOOK LOOKBOOK(1) (1).pdfBASLIQ CURRENT LOOKBOOK LOOKBOOK(1) (1).pdf
BASLIQ CURRENT LOOKBOOK LOOKBOOK(1) (1).pdf
 
The basics of sentences session 2pptx copy.pptx
The basics of sentences session 2pptx copy.pptxThe basics of sentences session 2pptx copy.pptx
The basics of sentences session 2pptx copy.pptx
 
Introduction to Nonprofit Accounting: The Basics
Introduction to Nonprofit Accounting: The BasicsIntroduction to Nonprofit Accounting: The Basics
Introduction to Nonprofit Accounting: The Basics
 
Advanced Views - Calendar View in Odoo 17
Advanced Views - Calendar View in Odoo 17Advanced Views - Calendar View in Odoo 17
Advanced Views - Calendar View in Odoo 17
 
Unit-IV- Pharma. Marketing Channels.pptx
Unit-IV- Pharma. Marketing Channels.pptxUnit-IV- Pharma. Marketing Channels.pptx
Unit-IV- Pharma. Marketing Channels.pptx
 
Interactive Powerpoint_How to Master effective communication
Interactive Powerpoint_How to Master effective communicationInteractive Powerpoint_How to Master effective communication
Interactive Powerpoint_How to Master effective communication
 
Call Girls in Dwarka Mor Delhi Contact Us 9654467111
Call Girls in Dwarka Mor Delhi Contact Us 9654467111Call Girls in Dwarka Mor Delhi Contact Us 9654467111
Call Girls in Dwarka Mor Delhi Contact Us 9654467111
 
fourth grading exam for kindergarten in writing
fourth grading exam for kindergarten in writingfourth grading exam for kindergarten in writing
fourth grading exam for kindergarten in writing
 
General AI for Medical Educators April 2024
General AI for Medical Educators April 2024General AI for Medical Educators April 2024
General AI for Medical Educators April 2024
 
Sports & Fitness Value Added Course FY..
Sports & Fitness Value Added Course FY..Sports & Fitness Value Added Course FY..
Sports & Fitness Value Added Course FY..
 
Accessible design: Minimum effort, maximum impact
Accessible design: Minimum effort, maximum impactAccessible design: Minimum effort, maximum impact
Accessible design: Minimum effort, maximum impact
 
APM Welcome, APM North West Network Conference, Synergies Across Sectors
APM Welcome, APM North West Network Conference, Synergies Across SectorsAPM Welcome, APM North West Network Conference, Synergies Across Sectors
APM Welcome, APM North West Network Conference, Synergies Across Sectors
 
1029-Danh muc Sach Giao Khoa khoi 6.pdf
1029-Danh muc Sach Giao Khoa khoi 6.pdf1029-Danh muc Sach Giao Khoa khoi 6.pdf
1029-Danh muc Sach Giao Khoa khoi 6.pdf
 
A Critique of the Proposed National Education Policy Reform
A Critique of the Proposed National Education Policy ReformA Critique of the Proposed National Education Policy Reform
A Critique of the Proposed National Education Policy Reform
 
Código Creativo y Arte de Software | Unidad 1
Código Creativo y Arte de Software | Unidad 1Código Creativo y Arte de Software | Unidad 1
Código Creativo y Arte de Software | Unidad 1
 
BAG TECHNIQUE Bag technique-a tool making use of public health bag through wh...
BAG TECHNIQUE Bag technique-a tool making use of public health bag through wh...BAG TECHNIQUE Bag technique-a tool making use of public health bag through wh...
BAG TECHNIQUE Bag technique-a tool making use of public health bag through wh...
 
Disha NEET Physics Guide for classes 11 and 12.pdf
Disha NEET Physics Guide for classes 11 and 12.pdfDisha NEET Physics Guide for classes 11 and 12.pdf
Disha NEET Physics Guide for classes 11 and 12.pdf
 
Key note speaker Neum_Admir Softic_ENG.pdf
Key note speaker Neum_Admir Softic_ENG.pdfKey note speaker Neum_Admir Softic_ENG.pdf
Key note speaker Neum_Admir Softic_ENG.pdf
 

Chapter 5 a

  • 1. Chapter 5 Large and Fast: Exploiting Memory Hierarchy
  • 2.
  • 3.
  • 4.
  • 5.
  • 6.
  • 7.
  • 8.
  • 9.
  • 10. Cache Example Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — Index V Tag Data 000 N 001 N 010 N 011 N 100 N 101 N 110 Y 10 Mem[10110] 111 N Word addr Binary addr Hit/miss Cache block 22 10 110 Miss 110
  • 11. Cache Example Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — Index V Tag Data 000 N 001 N 010 Y 11 Mem[11010] 011 N 100 N 101 N 110 Y 10 Mem[10110] 111 N Word addr Binary addr Hit/miss Cache block 26 11 010 Miss 010
  • 12. Cache Example Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — Index V Tag Data 000 N 001 N 010 Y 11 Mem[11010] 011 N 100 N 101 N 110 Y 10 Mem[10110] 111 N Word addr Binary addr Hit/miss Cache block 22 10 110 Hit 110 26 11 010 Hit 010
  • 13. Cache Example Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — Index V Tag Data 000 Y 10 Mem[10000] 001 N 010 Y 11 Mem[11010] 011 Y 00 Mem[00011] 100 N 101 N 110 Y 10 Mem[10110] 111 N Word addr Binary addr Hit/miss Cache block 16 10 000 Miss 000 3 00 011 Miss 011 16 10 000 Hit 000
  • 14. Cache Example Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — Index V Tag Data 000 Y 10 Mem[10000] 001 N 010 Y 10 Mem[10010] 011 Y 00 Mem[00011] 100 N 101 N 110 Y 10 Mem[10110] 111 N Word addr Binary addr Hit/miss Cache block 18 10 010 Miss 010
  • 15. Address Subdivision Chapter 5 — Large and Fast: Exploiting Memory Hierarchy —
  • 16.
  • 17.
  • 18.
  • 19.
  • 20.
  • 21.
  • 22.
  • 23. Example: Intrinsity FastMATH Chapter 5 — Large and Fast: Exploiting Memory Hierarchy —
  • 24.
  • 25.
  • 26.
  • 27. DRAM Generations Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — Year Capacity $/GB 1980 64Kbit $1500000 1983 256Kbit $500000 1985 1Mbit $200000 1989 4Mbit $50000 1992 16Mbit $15000 1996 64Mbit $10000 1998 128Mbit $4000 2000 256Mbit $1000 2004 512Mbit $250 2007 1Gbit $50
  • 28.
  • 29.
  • 30.
  • 31.

Editor's Notes

  1. Morgan Kaufmann Publishers 9 March 2010 Chapter 5 — Large and Fast: Exploiting Memory Hierarchy
  2. Morgan Kaufmann Publishers 9 March 2010 Chapter 5 — Large and Fast: Exploiting Memory Hierarchy
  3. Morgan Kaufmann Publishers 9 March 2010 Chapter 5 — Large and Fast: Exploiting Memory Hierarchy
  4. Morgan Kaufmann Publishers 9 March 2010 Chapter 5 — Large and Fast: Exploiting Memory Hierarchy
  5. Morgan Kaufmann Publishers 9 March 2010 Chapter 5 — Large and Fast: Exploiting Memory Hierarchy
  6. Morgan Kaufmann Publishers 9 March 2010 Chapter 5 — Large and Fast: Exploiting Memory Hierarchy
  7. Morgan Kaufmann Publishers 9 March 2010 Chapter 5 — Large and Fast: Exploiting Memory Hierarchy
  8. Morgan Kaufmann Publishers 9 March 2010 Chapter 5 — Large and Fast: Exploiting Memory Hierarchy
  9. Morgan Kaufmann Publishers 9 March 2010 Chapter 5 — Large and Fast: Exploiting Memory Hierarchy
  10. Morgan Kaufmann Publishers 9 March 2010 Chapter 5 — Large and Fast: Exploiting Memory Hierarchy
  11. Morgan Kaufmann Publishers 9 March 2010 Chapter 5 — Large and Fast: Exploiting Memory Hierarchy
  12. Morgan Kaufmann Publishers 9 March 2010 Chapter 5 — Large and Fast: Exploiting Memory Hierarchy
  13. Morgan Kaufmann Publishers 9 March 2010 Chapter 5 — Large and Fast: Exploiting Memory Hierarchy
  14. Morgan Kaufmann Publishers 9 March 2010 Chapter 5 — Large and Fast: Exploiting Memory Hierarchy
  15. Morgan Kaufmann Publishers 9 March 2010 Chapter 5 — Large and Fast: Exploiting Memory Hierarchy
  16. Morgan Kaufmann Publishers 9 March 2010 Chapter 5 — Large and Fast: Exploiting Memory Hierarchy
  17. Morgan Kaufmann Publishers 9 March 2010 Chapter 5 — Large and Fast: Exploiting Memory Hierarchy
  18. Morgan Kaufmann Publishers 9 March 2010 Chapter 5 — Large and Fast: Exploiting Memory Hierarchy
  19. Morgan Kaufmann Publishers 9 March 2010 Chapter 5 — Large and Fast: Exploiting Memory Hierarchy
  20. Morgan Kaufmann Publishers 9 March 2010 Chapter 5 — Large and Fast: Exploiting Memory Hierarchy
  21. Morgan Kaufmann Publishers 9 March 2010 Chapter 5 — Large and Fast: Exploiting Memory Hierarchy
  22. Morgan Kaufmann Publishers 9 March 2010 Chapter 5 — Large and Fast: Exploiting Memory Hierarchy
  23. Morgan Kaufmann Publishers 9 March 2010 Chapter 5 — Large and Fast: Exploiting Memory Hierarchy
  24. Morgan Kaufmann Publishers 9 March 2010 Chapter 5 — Large and Fast: Exploiting Memory Hierarchy
  25. Morgan Kaufmann Publishers 9 March 2010 Chapter 5 — Large and Fast: Exploiting Memory Hierarchy
  26. Morgan Kaufmann Publishers 9 March 2010 Chapter 5 — Large and Fast: Exploiting Memory Hierarchy
  27. Morgan Kaufmann Publishers 9 March 2010 Chapter 5 — Large and Fast: Exploiting Memory Hierarchy
  28. Morgan Kaufmann Publishers 9 March 2010 Chapter 5 — Large and Fast: Exploiting Memory Hierarchy
  29. Morgan Kaufmann Publishers 9 March 2010 Chapter 5 — Large and Fast: Exploiting Memory Hierarchy
  30. Morgan Kaufmann Publishers 9 March 2010 Chapter 5 — Large and Fast: Exploiting Memory Hierarchy
  31. Morgan Kaufmann Publishers 9 March 2010 Chapter 5 — Large and Fast: Exploiting Memory Hierarchy