Memory Barriers

Dennis Byrne [email_address] ,[object Object]

Defining the Problem Object connection = null; boolean initialized = false; // thread 1 writes twice // thread 2 reads twice connection = new Connection(); if(initialized) initialized = true; connection.use(); NullPointerException ?

Root Cause: Memory Latency ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Introduction Memory barriers, or fences, are a set of processor instructions used to apply ordering limitations on read and write operations .

Visibility is “kind of” important ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Classifying Memory Barriers ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Dekker’s Algorithm ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],// 2nd thread intentSecond = true; while (intentFirst) if (turn != 1) { intentSecond = false; while (turn != 1) {} intentSecond = true; } criticalSection(); turn = 0; intentSecond = false;

Consecutive Volatile Writes on Itanium 2 ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],The other side of the protocol ….

Consecutive Volatile Reads on Itanium 2 ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],One side of the protocol ….

Implicit Memory Barriers ,[object Object],[object Object],[object Object],[object Object],[object Object],Atomic CAS operation on x86 lock cmpxchg serializes pending memory operations

Avoiding Memory Barriers ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Memory Barriers ,[object Object],[object Object],[object Object]

Memory Barriers

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Memory Barriers