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Track A-Compilation guiding and adjusting - IBM
1. Compilation guiding and adjusting to hardware changes in Embedded Reconfigurable Architecture ( ) May 4, 2011 Ayal Zaks IBM Haifa Research Lab E A R
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4. Memory component Network component Processing component Monitoring Hardware scheduler LIBRARIES Applications OS (or software scheduler) C/C++/ Java compiler Power vs. Performance ARM, VEX, DSP, accelerators, etc. Crossbar, bus, NoC, etc. Multi-level caches, controllers, etc. Abstract overview of the platform E A R
5. Partners of Participant no. Participant organisation name Short name Country 1 (Coordinator) Technische Universiteit Delft TUD NL 2 Industrial Systems Institute ISI GR 3 Universita' degli Studi di Siena UNISI IT 4 Chalmers University CHALMERS SE 5 University of Edinburgh UEDIN UK 6 Evidence EVI IT 7 ST Microelectronics ST IT 8 IBM IBM IL 9 Universidade do Rio Grande do Sul UFRGS BR 10 Uppsala University UPP SE E A R
21. Contact information Visit http://www.era-project.eu for more information Coordinator: Stephan Wong (Delft University of Techology) [email_address] http://ce.et.tudelft.nl/~stephan/ IBM representative , Work Package 4 leader: Ayal Zaks (IBM Haifa Research Lab) [email_address] https://www.research.ibm.com/haifa/dept/svt/code_compiler.html
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Notas do Editor
Proebting was talking about performance; what about power/energy?? How can compilers help improve power? Tell me if you know..
This slide is quite self-explanatory
This slide shows the general overview of the ERA platform. Basically, there are different components for “processing”, “networking”, and “memories” that we can choose from in order to build the platform. On top, we want to be able to adapt to different applications by choosing from libraries of these components – an additional advantage is that we want to do this dynamically. For this, we need a hardware scheduler or an OS/software scheduler that works in tandem with the hardware scheduler. The monitoring block monitors for example the power and performance of the system and this information can be fed into the schedulers. Finally, we need a smarter compiler is better aware of the dynamic behavior of the platform.
This slides shows all the partners within the project.
This slide summarizes the slide with the figure of the ERA platform.
-mcpu: architecture (ISA); -mtune: micro-architecture Several PowerPC versions; code size, flexibility, switch versions at specific places in code
Memory params – static analysis of memory access patterns, temporal and spatial reuse Partition code into sections representing phases of distinct ILP/MEM
In the table, you can highlight the fact that we can parameterize the issue width of the roVEX processor and that different instantiations have different resource utilizations.
On this slide, we can see that with the same resources, we can instantiate different cores. 2 smaller ones to handle TLP or combine it into a big to exploit ILP. The idea in the ERA project is to be able to do this on-the-fly in a dynamic way manner.
This slide shows results on EDP (energy-delay product) measurements by varying the instruction window size (this has a clear relation with the parallelism of an application - ILP) and cache sizes. We see in this slide that when we increase the cache size, the EDP decreases. However, more interesting is the fact that the EDP product is similar (almost the same) with varying configurations – see the arrows pointing to different ILP-cache configurations. This means that we can optimize our design by changing the parameters and still achieve the same EDP. Please note that the information on this slide has not been published yet, so it is copyrighted!!
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