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Challenges in mixed signal
- 1. Challenges in mixed-signal SoCs Amir Sherman Semiconductors Technical Manager & Business Development Arrow Israel May 2 , 2012 1
- 2. PSoC 3 / PSoC 5 Platform Architecture May 2 , 2012 2
- 3. CPU Subsystem Clocking System MemoryPeripherals Dedicated Communication High Performance ARM Cortex-M3 ••• FlashSpeed USB device • Many memory with embedded CPU company Full Clock Sources Industry’s leading ECC • • ratio of SRAM data end • High 8 bidirectional Oscillator points + 1 control end point Internal Main to flash • Broad support for middleware and applications • • No external crystal required External clock crystal input • EEPROM • • Drivers inclock oscillator inputs External 100 DMIPS • Up to 80 MHz;PSoC Creator for HID class devices • Clock doubler output Powerful DMA Engine • • Full CAN 2.0b speed oscillator Enhanced v7low architecture: • Internal ARM • 24-Channel buffersMemory Access • • Thumb2DirectkHZ crystal buffers • 16 RX Instruction 8 TX input External 32 and Set • Access to all Digital MHz Analog Peripherals • Dedicated 48 and USB clock • • 16- and 32-bit Instructions (no mode switching) PLL output •• CPU master or simultaneous access to independent I2C and DMA slave • SRAMClock Dividers 16-bit blocks up to 400 kbps • 32-bit ALU; Hardware multiply and divide • Data rate • • Additional I2C slaves may be implemented in UDB 8 Digital • Single Analog On-Chip cycle 3-stage pipeline; Harvard architecture • array 4 Debug and Trace • PSoC Creator Configuration Wizard 8051 • Industry standard JTAG/SWD (Serial Wire Debug) • • PSoC Creator auto-derive clocking source/dividersare New peripherals will be added as family members • • On chipbase of existing Ethernet, HS USB, USB Host… Broad trace added to the platform: code and support • • NO MORE ICE 33 MIPS Up to 67 MHz; • Single cycle instruction execution May 2 , 2012 3
- 4. CPU Subsystem Power Management • Industry’s Widest Operating Voltage • 0.5V to 5.5V with full analog/digital capability • High Performance at 0.5V • PSoC 3 @ 67 MHz; PSoC 5 @ 72 MHz • 3 Power Modes (Active, Sleep and Hibernate) May 2 , 2012 4
- 5. Designed for Low Power On-board DMA Controller Direct memory transfer between peripherals offloads CPU operation, Highly configurable clock lowering power consumption tree Flexible, automated clock gating. Universal Digital Blocks Implement features in hardware that reduce CPU processing requirements, lowering power consumption Cached Operations Execution from flash memory is improved by caching instructions (PSoC 5 only) Precise CPU frequencies PLL allows 4,032 different frequencies; tunable power Integrated Analog, Digital and consumption Communication Peripherals Reduce external component counts and lower overall system power consumption May 2 , 2012 5
- 6. Low Power Modes Digital Analog Current Current Code Clock sources Wakeup Reset Power mode resources resources (PSoC 3) (PSoC 5) execution available sources sources available available 1.2 mA 2 mA Active Yes All All All N/A All @ 6MHz @ 6MHz IO, I2C, XRES, LVD, Low Speed and RTC, Sleep 1 uA 2 uA No I2C Comparator WDR 32 kHz Osc sleep timer, comparator Hibernate 200 nA 300 nA No None None None IO XRES, LVD Power Management Enabled in PSoC Creator • Provides easy to use control APIs for quick power management • Allows code and register manipulation for in-depth control May 2 , 2012 6
- 7. Digital Subsystem Optimized 16-bit Block Array (UDBs) Universal Digital Timer/Counter/PWM Blocks • • Provides nearly all of the features of CPU Flexibility of a PLD integrated with a a UDB based timer, counter, or PWM • • PSoC Creator provides easy access to these Provides hardware capability to implement flexible blocks components from a rich library of pre-built, 32-bit PWM • Each block may be configured as either a full documented, and characterized components GP Logic featured 16-bit Timer, Counter, or PWM in PSoC Creator 16-bit PWM UART #1 • Programmable options GP Logic GP UART • PSoC Creator willreset, capture,place, and pin Clock, enable, synthesize, kill from any UART #3 • Logic #2 or digital signal on chip route components automatically. GP • Independent control of terminal count, LCD Segment Drive interrupt, compare, reset, enable, capture, and Logic GP Logic • Finekill synchronization configuration granularity enables high I2C Slave • silicon utilization Plus • Configurable to measure pulse widths or 16-bit Shift Reg. SPI Master GP Logic • DSI routing mesh allows any function in the periods • Buffered PWM with dead any other UDBs to communicate withband and killon-chip function/GPIO pin with 8- to 32-bit data buses May 2 , 2012 7
- 8. Analog Subsystem Configurable Analog System • Flexible Routing: All GPIO are Analog Input/Output • +/- 0.1% Internal Reference Voltage • Delta-Sigma ADC: Up to 20-bit resolution • 16-bit at 48 ksps or 12-bit at 192 ksps • SAR ADC: 12-bit at 1 Msps • DACs: 8 – 10-bit resolution, current and voltage mode • Low Power Comparators • Opamps (25 mA output buffers) • Programmable Analog Blocks • Configurable PGA (up to x50), Mixer, Trans-Impedance Amplifier, Sample and Hold • Digital Filter Block: Implement HW IIR and FIR filters • CapSense Touch Sensing enabled May 2 , 2012 8
- 9. Programmable Routing/Interconnect Input / Output System • Three types of I/O • GPIO, SIO, USBIO • Any GPIO to any peripheral routing • Wakeup on analog, digital or I2C match • Programmable slew rate reduces power and noise • 8 different configurable drive modes • Programmable input threshold capability for SIO • Auto and custom/lock-able routing in PSoC Creator Up to 4 separate I/O voltage domains • Interface with multiple devices using one PSoC 3 / PSoC 5 device May 2 , 2012 9
- 10. PSoC 3 / PSoC 5 Platform Architecture May 2 , 2012 10
- 11. Open PSoC Creator May 2 , 2012 11
- 12. Step 1: How is easy to Make a Design based on PSOC with PSoC Creator May 2 , 2012 12
- 13. Step 2: Create a New Project May 2 , 2012 13
- 14. Step 3: Place/Configure Digital Pin May 2 , 2012 14
- 15. Step 5: Add main.c Code Step 4: Configure PSoC I/O May 2 , 2012 15
- 16. Step 6-7: Build Project & Program/Debug Step 8: Debug May 2 , 2012 16
- 17. PSoC 5:PSoC Creator Design Flow Create a new project Select the platform Name the design Select the device* Select the sheet template* PSoC Creator * Optional steps Design Canvas May 2 , 2012 17
- 18. Component Catalog Catalog Folders Analog ADC Amplifier DAC Digital Registers Functions Logic Adding Components Communication Display to a Design System Catalog Preview Datasheet access May 2 , 2012 18
- 19. Component Configuration Pins, Logic and Clock Components Double-click to open component configuration dialogs May 2 , 2012 19
- 20. Component Data Sheets Contents: • Features • General description of component • When to use component • Input/Output connections • Parameters and setup • Application Programming Interface • Sample firmware source code • Functional description • DC and AC electrical characteristics May 2 , 2012 20
- 21. Design-Wide Resource Manager (.cydwr) Clocks Interrupts • Set priority and vector DMA • Manage DMA channels System • Debug, boot parameters, sleep mode API generation, etc. Directives • Over-ride placement defaults Pins • Map I/O to physical pins and ports • Over-ride default selections May 2 , 2012 21
- 22. Clock Configurations System Clocking Tree Clocks are allocated to slots in the clock tree • 8 digital, 4 analog Clocks have software APIs Reuse existing clocks to preserve resources May 2 , 2012 22
- 23. Connecting Components Pin Editor May 2 , 2012 23
- 24. Build Hardware Design May 2 , 2012 24
- 25. Build Process Generate a Configuration API Generation • Design Elaboration Compilation • Netlisting Configuration Generation • Verilog Configuration Verification • Logic Synthesis • Technology Mapping • Analog Place and Route • Digital Packing • Digital Placement • Digital Routing • <…there’s more…> May 2 , 2012 25
- 26. Supported Compilers Free Bundled compiler options PSoC 3: Cypress-Edition Keil™ CA51 Compiler Kit PSoC 5: GNU/CodeSourcery Sourcery G++™ Lite No code size restrictions, not board-locked, no time limit Fully integrated including full debugging support GNU Upgrade, more optimization/compiler-support options PSoC 3: Keil CA51™ Compiler Kit PSoC 5: Keil RealView® Microcontroller Development Kit Higher levels of optimization Direct support from the compiler vendor Upgrade Compiler Pricing Set and managed by our 3rd party partner, Keil Already own these compilers? No need to buy another license! May 2 , 2012 26
- 27. Integrated Debugger JTAG and SWD connection • All devices support debug • MiniProg3 programmer / debugger Control execution with menus, buttons and keys Debugger Windows Full set of debug windows • Locals, register, call stack, watch (4), memory (4) • C source and assembler • Components Set breakpoints in Source Editor May 2 , 2012 27
- 28. PSoC Development Kit (CY8CKIT-050) • Supports all PSoC architectures via processor modules • Integrated support of all required and optional chip connections • MiniProg3 should not supply power to PSoC Development Kit Free May 2 , 2012 28
- 29. Amir Sherman Semiconductors Technical Marketing Manager & Business Development Arrow Israel asherman@arroweurope.com 03-9203465 052-2240811 May 2 , 2012 29
Notas do Editor
- 4 Main components of the PSoC Platform: CPU Subsystem, Digital Subsystem, Analog Subsystem and Programmable Routing and Interconnect Let’s step through these…first, the CPU Subsystem
- PSoC 5 at 72 MHz between 0.5v to 2.7v and back up to 80MHz from 2.7v to 5.5v
- Clock is automatically shut down for non-functioning parts…automated clock gating Keys DMA UDBs Shutdown CPU when/if not needed Setup story of our low-power approach to design
- PSoC1 Power: Active: (2mA @ 6MHz) Sleep: 3uA Hibernate: N/A
- What a UDB is (high-level)…step through the animation Intelligent routing Efficiency of the UDBs (part/pieces of each UDB can be used sep.) Custom logic Standard peripherals+custom logic What’s the logic equivalent…~500-700 gates per UDB, 24 UDBs in the larger chips Suggested Flow: (a) go through 5 major points elaborating with info from slide notes. (b) Talk though two step animation. Step 1) PSoC Creator automatically places and routes components from PSoC Creator component library onto the UDB array and DSI routing mesh. Step 2) Customer control logic you may have implemented in verilog can take advantage of used used PLDs in UDBs (no waste). Point out the drawing is only conceptual Flexibility of a PLD integrated with a CPU. With a discrete PLD or FPGA logic would be consumed creating a bus interface to your MCU, not so in PSoC. Details on the following slide. Provides access to a rich library of pre-build, documented, and characterized components in PSoC Creator For example, UART, SPI, logic gages (AND, OR, NOR, etc) quadrature decoders, and more. The UDB array may also be used to implement additional I2C, timer, counter, and PWM functions if dedicated and optimized peripherals have already been used. Fine configuration granularity enables high silicon utilization. When we say that a component uses 2 UDBs it is unlikely that 100% of those 2 UDBs are actually used. For example, 2 DUBs maybe used use to implement a 16-bit shift register, but, the PLD in those UDBs are not used. PSoC Creator keeps track of this usage information allow for example a users custom Verilog to use the PLDs that are not used by the 16-bit shift register. This is what we mean by fine granularity of the configuration. Supports user generated Verilog control logic (PSoC Creator takes care of synthesis, placement, and routing.). DSI Routing mesh allows any function in the UDBs to communicate with another on-chip function or any GPIO pin. NOTE: PSoC Creator today does not have a 32-bit PWM component, however silicon supports this capability. A customer or Cypress could create a 32-bit PWM component that will run inside the device.
- Some chips with lots or less analog… Roadmap to analog filtering using the prog-analog blocks Use separate module and details from SCON content Key message is that this is portfolio of analog – scales with various products The PSoC3/5 architecture has a huge portfolio of analog IP. Exact configuration depends on the product family. 20-bit Del Sig samples at 180 sps
- That is the PSoC3/5 Platform Architecture/Summary.
- The Advanced button allows for selection of sheet template as well as device selection. From the Advanced button the device selector maybe launched. Not really important to make your device selection here, just the platform selection (PSoC3 or PSoC5) is what’s required…you can change your device at any time…including platform, but starting with one platform will establish what components you have to begin with.
- Generates component APIs
- The first task of the build process is to create a configuration of your device. The steps to achieve this are: Elaboration, Netlisting, Verilog, Logic Synthesis,VH2, Tech Mapping, Analog Place and Route, Digital Packing, Digital Placement, Digital routing,