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Analyzing Chips in a System Context
- 1. Analyzing Chips in a System Context Srdjan Djordjevic May 2, 2012 Senior Applications Engineer srdjand@sigrity.com May 2, 2012 1
- 2. ?Why Analyze Chips in a System Context Red = Chip Only May 2, 2012 Blue = Includes System-Level PDS 2
- 3. Voltage Noise Transfer System-Level Effects Can Dominate Chip Alone Chip with Package Chip Package High impedance • Low impedance • Localized voltage noise • Global voltage noise effects • effects :Result The low-loss power distribution system of the package readily .transfers voltage noise effects to other on-chip circuits May 2, 2012 3
- 4. Necessity of Fully Considering System-Level Noise ((Example – SSO Simulation Needed Accuracy = Risk Avoided Simulation with all power delivery effects Oversimplification = Risk Simulation assuming ideal power delivery network Simulation with partial power delivery effects May 2, 2012 4
- 5. Chip-Package Co-Simulation Flow (Chip/Package Co-Simulation: Enabling 2.5D IC (including silicon interposers( and 3D IC projects (including TSVs .with a focus on frequency domain power delivery network (PDN( analysis and EMI analysis May 2, 2012 5
- 6. Frequency Domain Chip / System Co- Simulation ((BGA / SiP / 2.5D IC / 3D IC :Chip Data :Package / System Data LEF / DEF … GDS … GUI to .SPD Layout Databases to .SPD Circuit Linkage with MCP .SPD or models May 2, 2012 6
- 7. Multi-Die / Package Floorplanning LEF LEF DEF DEF Die Data Verilog Verilog Outputs for Die pads Die pads Physical Implementation Pad-ring Pad-ring Die1 data data Device & Connection Planning Die2 Package Data AIF UPD Die1 ASCII pin info Hierarchical data Package ASCII net list preparation with automated net mapping GUI Feasibility (ex: Bump, RDL Wirebond) May 2, 2012 7
- 8. IO Planning and Multi-die Floorplanning ((2.5 D with Silicon Interposer Slice 1 Slice 2 Die Silicon Interposer BGA PCB Device Data Source BGA BGA.txt from Cadence APD Si Interposer Created on-the-fly Die Slice 1 LEF / OrbitIO IOview Die Slice 2 ASCII data May 2, 2012 8
- 9. Chip-Centric Analysis ((pre- & post layout-frequency & time domain LEF/DEF GDS GUI Power Grid Device Parasitic Current Profile Extraction Extraction Extraction Power Model IO Model Time-Domain Frequency-Domain Power Extraction Extraction Co-simulation Co-simulation Planner ((inc. TSV ((inc. RDL 2D/3D Transient S/Y/Z SPICE SPICE SPICE Waveforms Parameters Netlist Netlist Netlist May 2, 2012 9
- 10. Frequency Domain Chip / System Co-Simulation May 2, 2012 .Assessment of various decap options 10
- 11. On-Chip Decoupling Capacitors Case Example 5nF on-chip decap inserted 5nF on-chip No on-chip decap decap May 2, 2012 11
- 12. Frequency Domain EMI Analysis ((Chip-Level Input for System-Level Results Far Field Radiation Near Field Radiation May 2, 2012 12
- 13. Enabling Chip/System Power Co-simulation distributed :Chip PDN models can Be at a range of abstraction levels from lumped to distributed - (Vary from 2-node to N-nodes (N = number of physical pins - (Have 1 to M current sources (M can be larger than N - lumped 1 M chip 1 N package VRM board May 2, 2012 13
- 14. Model Connections to Support Chip / System Simulation inc. RDL in IO model Inc. TSV in power model Chip(s( IO/Power Chip(s( IO/Power RLCK Network and SPICE Model SPICE Model Transient Current Sources XcitePI Spatially Distributed Interposer (or 3DIC( IO/Power SPICE Model RLCK Network & XtractIM PowerSI BGA IBIS, SPICE or S-parameter Model OptimizePI & other Sigrity PCB S-parameter or SPICE Model Analysis Products May 2, 2012 14
- 15. Open Model Connection Protocol Intelligent and automated model connections to .save time and reduce errors May 2, 2012 15
- 16. !Thank You May 2, 2012 16
Editor's Notes
- May 29, 2012
- Challenge = How to identify power delivery network issues including chip level problems that do not show up until the die is incorporated in a package due to coupling associated with package planes. System-level tradeoffs enable you to maximize performance and/or reduce cost. Also reliably balance design margins throughout system. System PDN performance strongly influences on-chip PDN performance power noise propagation across chip, through package. On-chip and chip/package resonances system PDN analysis defines requirement of On-Die Capacitance (ODC) Upper right = Location-dependent Impedance Profile For IO Chip Cells May 29, 2012
- Chip = Hi impedance due to highly resistive material v.s Package = Low impedance. This results in chips having high-loss and packages having low-loss. Chip level information … ~25% impact Include power information (from XcitePI, Apache, Cadence) System level information … ~75% impact Combine package and PCB layout files if you have access to them Make intelligent simplifications in PowerSI port selection Selected signals will be included along with all related power / ground structures May 29, 2012
- Bottom image – accuracy needed and Sigrity’s default. Upper left – result with circuit solver alone. Even if the product is sold as “doing S-parameters and PI” it is not accurate. Upper right a little more accuracy gained by applying some estimates of non-ideal PDS behavior showing some noise. Both of the above simulations oversimplify and give false confidence. Simulation with partial power delivery effects = “transmission line mode” The presence of non-plane power/ground net parasitics has a non-negligible effect on the results power plane noise still exists at devices linked to pads/vias this same level of noise is still reflected in the signals observe the switched signal ripple is extremely similar to the tied-high/low signal line noise AEs and users intuitively expected an “Ideal Power/Ground” style of operation from “Transmission Line Only” analysis Circuit analysis based EDA tools will behave very similar to Ideal Power/Ground analysis mode We are able to much more effectively demonstrate to the market the importance of not relying on ideal power/ground analysis techniques if we also remove the non-plane parasitics Plane resonance impacts signal performance Proximity coupling and power plane noise must both be considered Return current issues dominate in SSN effects SSN will can seriously underestimated by SI tools SSN & EMI also link About this simulation 16 bit memory Current DDR designs are likely even more susceptible Simulation time is modest
- Co-Simulation methodology in the frequency domain. Generate off-chip model by PowerSI (S-parameter model) or XtractIM (RLC or broadband circuit model) Perform on-chip power analysis by XcitePI, together with the off-chip model Inherently system-aware Application-focused modules Supports early design flow analysis and extraction Both time and frequency domain co-simulation Faster and more accurate Compute frequency-dependent impedance and S/Y/Z circuit-parameters of IC blocks and IO cells accounts for package models over broadband frequencies Assess impact of decoupling capacitors on-chip and throughout entire system Identify non-uniform performance between different blocks on power supplies and perform what-if analysis to explore design improvements Identify and visualize chip self resonance or chip/package resonances and investigate how to reduce or eliminate May 29, 2012
- Co-Simulating a Fully Distributed Chip and Package Utilize simplified approach to link models and manage abstraction. XcitePI is a chip/system co-simulation environment that also provides Chip Power and Chip IO models for system-level analysis XcitePI provides application-focused capabilities to support a broad set of PI and SI design tasks XcitePI uniquely supports a broad class of technologies RDL, TSV, power-aware SSO analysis Inherently system-aware Application-focused modules Supports early design flow analysis and extraction Both time and frequency domain co-simulation Faster and more accurate Frequency domain simulation capabilities: Compute frequency-dependent impedance S/Y/Z circuit-parameters of IC blocks and IO cells (accounts for package models over broadband frequencies). Assess impact of decoupling capacitors on-chip and throughout the entire system. Identify non-uniform performance between blocks on power supplies and perform what-if analysis to explore design improvements. Identify and visualize chip self resonance or chip/package resonances and investigate how to reduce or eliminate. May 29, 2012
- Import silicon and package data using standard and generic formats RF, analog, digital content Preliminary or final versions Update data as new versions become available In cases where data is missing or incomplete, devices can be instantiated on-the-fly using parametric definition Enables floorplanning to start at a high levels of abstraction then transition to detailed content as it become available Die 1 and 3 are located on the BGA substrate – same level in hierarchy tree Die 2 is located on the Die 1 substrate since it’s a stacked-die configuration All three die were imported from separate data sources Hierarchy Management used to establish relationships between die and BGA 3 Die SiP design Die 1 and 3 are located on the BGA substrate – same level in hierarchy tree Die 2 is located on the Die 1 substrate since it’s a stacked-die configuration All three die were imported from separate data sources Die 1 and 3 using their respective LEF/DEF files including tech.lefs Die 2 using ASCII die pin data Hierarchy Management used to establish relationships between die and BGA Drag & drop in Hierarchy Manager Interactive placement on canvas Output of individual designs for physical implementation May 29, 2012
- A unified planning environment to coordinate device placement and net assignments across all substrates Multi-substrate support with automatic hierarchy management Easily import and export data on an individual substrate basis Connection planning and optimization using top-down, bottom-up, or middle-out methodologies Net management and correlation for complete system Platform for design reuse and technology exploration Easily transition from high level abstractions using best available data then refine and optimize as detailed content emerges Openness and extensibility are key characteristics with the intention of users implementing custom or proprietary functionality May 29, 2012
- Example LEF/DEF import – Example for a flip-chip design = 3 LEF files / 126 DEF files (11GB), 10 metal layers, 3,750 bumps (1,824 VDD / 1906 VSS), 110 top level circuit placements, 15M decaps of 10 types. Example GDS Import – Example for a flip-chip design = 1.56 GB file, 12 metal layers, die size 12cm x 12cm. Example GUI Editor – Editor window to set-up design attributes. Useful for pre-layout as well as post layout. Easy to generate the power grid and circuit from scratch. Easy to make changes for what-if analysis. Power Model Extraction – used for system-level power analysis using Sigrity or 3 rd party tools Distributed power grid model (R, L, C, K) TSV models (if present) Device parasitic models (effective C and leakage) Stimulus current profiles Model of user-defined resolution (potentially very high resolution … each bump could have a distinct circuit terminal) Reduced-order model of concise circuit size (compressed from the model of the entire multi-layer power-ground grid) Chip IO Model extraction – Used in system-level signal integrity analysis using Sigrity or 3 rd party tools including power-aware SSO simulation Distributed IO power grid and IO net modules (R, L, C, K) … RDL may be included in extraction Consider all parasitics … self parasitics for both signals and power, mutual parasitics within and between signals and power Model of user defined resolution … potentially very high resolution (each bump could have a distance circuit terminal) Reduced-order model of concise circuit size … compressed frommodel of the entire multi-layer power-ground grid Power Planner Provides a graphical user interface for high level specification of early chip power delivery network (PDN) information. Power Planner supports package/board system-centric PDN simulation of the entire system prior to final chip design being available Efficient what-if analysis of entire PDN, especially in the early design stage Power Planner models may be incorporated with Sigrity or third party system level analysis tools to perform DC, AC and transient analysis of entire PDN systems Power Planner flow Specify chip design information (chip dimensions, block definitions including device and power grid models, optional Power Grid model generation with netlist input Specify blocks (block size, net name, device model with generation wizard, power-grid model with generation wizard) Define additional circuits (decoupling capacitors, current sources, etc.) Generate a distributed MxN mesh-based chip power model Apply chip power model to perform AC, transient and DC analysis of the entire PDN system in Sigrity or third party system analysis tools with direct access of Power Planner from Sigrity system-level analysis tools May 29, 2012
- Study one port impedance in different system decap set-up conditions May 29, 2012
- Step #1 - Takes a merged Sil Power Model on package DIE circuit with current profiles Step #2 – Obtain a FD periodic current source (through fourier transfer) Step #3 – System Level Outputs – Far Field Radiation / near field radiation May 29, 2012
- A typical chip / package / board system will have a lot of connections. Consider: Chip … N-node chip model Package … 10 layer BGA Top 400 VDD bumps 2007 VSS bumps Bottom 98 VDD balls 227 VSS bals Board 24 layers May 29, 2012
- May 29, 2012
- The specification for Sigrity’s model connection protocol is freely available without charge or license. A distributed mesh-based chip power model SPICE netlist file MCP header for automated connectivity Model contains block definitions block placements all decap and other circuit placements Advantages: Open Automates connections to avoid errors Intelligent enough to understand appropriate orientation (and flipping) X,Y information can be explicitly needed to support flows (added in 1.1) Model Connection Protocol Connecting circuit models and / or physical layouts automatically Chip - Package - Board ASCII SPICE compatible format Sigrity produced models 3 rd party models with MCP support Flexible handling of Multiple circuit connections within one model Mapping between lumped circuit nodes and physical pins May 29, 2012
- May 29, 2012