1. EE 290C
CMOS Analog Design Using
All-region MOSFET Modeling
Lecture 2: Fundamentals of the MOSFET model
( Two- and three- terminal MOS structures)

2. Semiconductors
Four types of charge are present inside a
semiconductor: the fixed positive charge of ionized
donors, the fixed negative charge of ionized
acceptors, the positive mobile charge of holes, and
the negative mobile charge of electrons.
We consider all donors and acceptors ionized
+ −
N D = N D and N A = N A
On this basis, the net positive charge density ρ is
ρ = q ( N D − N A + p − n)
CMOS Analog Design Using All Region MOSFET Modeling
2

3. Boltzmann’s Law-1
In equilibrium electrons and holes follow Boltzmann’s
law and their concentrations (number per unit
volume) are proportional to -( Energy / kT )
e
k=1.38x10-23 J/K is the Boltzmann constant
T is the absolute temperature in Kelvin.
electron and hole densities in equilibrium are related
to electrostatic potential φ by
q (φ 1−φ 2 )
p (φ 1) −
=e kT
p (φ 2)
q=1.6x10-19 C is the electron charge
3
CMOS Analog Design Using All Region MOSFET Modeling

4. Boltzmann’s Law-2
n0 and p0 equilibrium electron and hole
concentrations in the neutral bulk (φ=0 )
qφ qφ
−
−u
p = p0 e = p0 e
kT
= n0 eu
n = n0e kT
u = φ / φt normalized electrostatic potential
φt = kT / q is the thermal potential
ni the concentration of electrons (and holes)
in an intrinsic semiconductor, the mass-action
law is np = ni2
CMOS Analog Design Using All Region MOSFET Modeling
4

5. Example: Calculate the junction built-in
potential for a Si pn junction with NA = 1017
atoms/cm and ND = 1018 atoms/cm3 ,T=300K
In equilibrium, if we choose the potential origin φ = 0
where the semiconductor is intrinsic (i.e., where
p0=n0=ni)
− φ / φt
p =ne n0 = ni eφ / φt
0 i
φn− region / φt
Far from the junction
n0 ≅ N D = ni e
on the n-side
Far from the junction −φ p − region / φt
p0 ≅ N A = ni e
on the p-side
The built-in potential is given by
  NA 
 ND  ND NA 
 −  −φt ln    = φt ln 
φbi = φn − region − φ p − region = φt ln  
 ni   ni 2 
 ni   

φbi ≅ 26 ⋅ ln (1015 ) ≅ 900 mV 5
CMOS analog design using all-region MOSFET

6. The Two-Terminal MOS Structure
6
CMOS Analog Design Using All Region MOSFET Modeling

7. The Ideal Two-Terminal MOS Structure
(VFB=0)
Aε ox
=
C ox
t ox
QG M
QG capacitor area A, oxide
VG − φs =
thickness tox and permittivity of
Cox O oxide εox
+
S
QC Cox ε ox
QG
φs ′ ′
QG = Cox = =
A A tox
_
QG + QC = 0 ′
QC
VG = φs −
′
Cox
7
CMOS Analog Design Using All Region MOSFET Modeling

8. Example
(a) Calculate the oxide capacitance per unit area
for tox= 5 and 20 nm assuming εox = 3.9ε0, where
ε0= 8.85·10-14 F/cm is the permittivity of free
space. (b) Determine the area of a 1pF metal-
oxide-metal capacitor for the two oxide
thicknesses given in (a).
Answer: (a) =690 nF/cm2 = 6.9 fF/µm2 for tox=5 nm
and = 172 nF/cm2= 1.7 fF/µm2 for tox= 20 nm. The
capacitors have areas of 145 and 580 µm2 for oxide
thicknesses of 5 and 20 nm, respectively.
CMOS Analog Design Using All Region MOSFET Modeling
8

9. The Flat-Band Voltage
In equilibrium (with the two terminals shortened/open), the
contact potential between the gate and the semiconductor
substrate of the MOS induces charges in the gate and the
semiconductor for VGB=0.
Charges inside the insulator and at the semiconductor-insulator
interface also induce a semiconductor charge at zero bias.
The effect of the contact potential and oxide
charges can be counterbalanced by applying a
gate-bulk voltage called the flat-band voltage VFB.
′
QC
= φs −
VG − VFB
′
Cox
CMOS Analog Design Using All Region MOSFET Modeling 9

10. Example
(a) Determine the expression for the flat-band voltage of
n+ polysilicon-gate on p-type silicon (b) Calculate the flat-
band voltage for an n+ polysilicon-gate on p-type silicon
structure with NA = 1017 atoms/cm-3.
Answer:
(a) In equilibrium, by analogy with an n+ p junction, the
potential of the n+-region is positive with respect to that of
the p-region The flat-band condition is obtained by
applying a negative potential to the n+ gate with respect to
the p-type semiconductor of value
 NA 
VFB _ n + p = −φbi _ n + p = −0.56 V − φt ln  
ni 

VFB = −0.56 V − φt ln (107 ) = −980 mV
(b)
CMOS Analog Design Using All Region MOSFET Modeling 10

11. Operation Regimes of the MOSFET:
Accumulation (p-substrate)
VGB < V FB
′
QC > 0
G
φs < 0
QG
-----------
Qo
+ + + +
++++++++++++++ Holes +
VGB
QC
accumulate in the P
semiconductor
surface
B
CMOS Analog Design Using All Region MOSFET Modeling 11

12. Operation Regimes of the
MOSFET: Depletion (p-substrate)
VGB > V FB
′
QC < 0
G
0 < φs < φF
QG
+ ++++++++
Qo
Holes evacuate from the P
+ + + +
- -- - - - - -- -
VGB semiconductor surface and
QC
-
--- acceptor ion charges
- become uncovered
φF = Fermi potential ( to be defined)
B
CMOS Analog Design Using All Region MOSFET Modeling 12

13. Operation Regimes of the MOSFET:
Inversion (p-substrate)
VGB > V FB
′
QC < 0
G
φs > φF
QG
+ ++++++++
Qo
+ + + +
- -- - --- - -- -
VGB
Q electrons approach the
C
-- -- - - - - - surface!
--
-
B
CMOS Analog Design Using All Region MOSFET Modeling 13

14. Inversion for p-Type Substate
volume charge density inside the semiconductor:
−u u
ρ = q( p0e − n0e + n0 − p0 )
depletion of holes prevails over electron charge when
−u
> n0 e or
u
p0 e 2
φt φt
p0 p0 p0
φ < ln( ) = ln( 2 ) = φt ln( ) = φF
2 2
n0 ni ni
φ >φF the concentration of minority carriers (n) becomes
higher than that of majority carriers (p); inversion
CMOS Analog Design Using All Region MOSFET Modeling 14

15. Small Signal Equivalent Capacitive
Circuit of the MOS Capacitor
′
dQC 1
′
Cgb = − =
′ ′
dQG dQC ′ d φs
dQC 1
′
C gb = =− d φs − − +
dVG dVG ′ ′ ′
Cox dQC Cox
1
′
C gb =
1 1
+
′ ′
Cc Cox
′ ′
Cc = − dQC dφs
d ( QB + QI′ )
′
′ = Cb + Ci′
′
Cc = −
dφs CMOS Analog Design Using All Region MOSFET Modeling 15

16. Main Approximation for Compact
Modeling: Charge-Sheet Model
φ = φs
Minority carriers are at the interface Si-SiO2 where
dQI′ QI′
′ ∝ eφs /φt
QI Ci′ = − =−
φt
dφs
Charge-sheet + depletion
approximation for the bulk charge
QB ≅ −qNAxd = − 2qεs NA (φs −φt )
′
′
γ = 2qε s N A / Cox
2qε s N A ′
γ Cox is the body-effect
′
Cb ≅ = coefficient
2 φs − φt 2 φs − φt 16
CMOS Analog Design Using All Region MOSFET Modeling

17. The Three-Terminal MOS Structure
Carrier concentrations in Si
VG
VC substrate follow Boltzmann’s
law:
n, p ∝ exp(-Energy/kT)
p
n+
φS
The origin of potential φ is taken deep in the bulk
q (φ −VC )
qφ
−
= n0 eu −uC
= p0 e − u ;
p = p0 e n = n0 e
kT kT
electrons are no longer in equilibrium
pn = ni2 e − uC = ni2 e −VC / φt
with the holes, due to the bias of the
source-bulk junction VC
CMOS Analog Design Using All Region MOSFET Modeling 17

18. Small Signal Equivalent Capacitive
Circuit of the 3 Terminal MOS
dQI′ ( Cb + Cox ) Ci′
′ ′
=
dVC Ci′ + Cb + Cox
′ ′
 1
1
dQI′  +  = dVC
 Cox + Cb Ci′ 
′ ′
Approximations:
1) depletion capacitance per unit area is constant along the
channel and is calculated neglecting inversion charge
Ci′ = −QI′ / φt
2) Charge sheet model
CMOS Analog Design Using All Region MOSFET Modeling 18

19. The Linearization Point φsa
φsa = φs
Determination of ′
QI =0
′
QB
potential balance = φsa − = φsa + γ φsa − φt
VG − VFB
′
Cox
γ2 γ VG
φsa − φt = VG − VFB − φt + −
4 2
′
Cox
QI′ = 0
_
+
φs = φsa
′
dφsa Cox 1
Ci′ = 0
= = _
′ ′
dVG Cox + Cb n ′
′ QB
Cb
+
CMOS Analog Design Using All Region MOSFET Modeling 19

20. Example
For tox = 5 nm and 20 nm determine the minimum doping NA for which the
slope factor n < 1.25 at φsa = 2φF.
Answer: For φsa=2φF
2qε s N A 2qε s N A
′
Cb
≅ 1+ = 1+
n =1+
′ ′ ′
2Cox φsa 2Cox 2φF
Cox
2
Thus, for n=1.25
( 0.25) 2φF 4Cox
′2
NA=
2qε s
where φF is a weak (logarithmic) function of NA. Using 2φF = 0.8 V for the
first calculation, we obtain after two iterations that NA> 4.9x1015 atoms/cm-3
for tox=5nm, and NA > 2.3·1014 atoms/cm-3 for tox=20 nm.
CMOS Analog Design Using All Region MOSFET 20
Modeling