4. 34 cycles to capture digital dataFigure 6.2: The simulated waveform of ADC data capture<br />The following waveform shows the calculation of Vin. As the ADC is negative data, 2’s complement need to be perform before the calculation of Vin. <br />The captured ADC data is hex “3FFF”, signed bi is 1, 2’s complement conversion is performed and result “0001” in hexadecimal.<br />Figure 6.3: Waveform of getting ADC data<br />The computed value VIN is ready for binary to BCD conversion.<br />Vin =125, that is 1.25V of input signal<br />Figure 6.4: Waveform of computing VIN<br />The following waveform shows that BCD code 125 is ready for the LCD displaying.<br />BCD3 is “0”, BCD2 is “1”, BCD1 is “2”, BCD is “5”<br />Figure 6.5: Waveform of getting BCD data format<br />The following waveform is a continuous loop to read data, calculate VIN and decode into BCD format.<br />Figure 6.6: Overall waveform<br />Chapter 7 Hardware Realization<br />7.1 DC Voltage Measurement Verification<br />To verify the functionality of DC volt meter, a AAA battery of 1.5V is connected the ADC VINA and GND as show in the Figure 7.1.<br />DMMCOM+VAAA Battery (1.5V)<br />Figure 7.1: DC Voltage Measurement Setup<br />AAA BatteryDMM ReadingMy Single Volt Meter Reading1.5V1.483V1.462V<br />Table 7.1: DC Voltage Measurement<br />7.2 RMS Sine Wave Measurement Verification <br />To verify the functionality of RMS functions for sine wave measurement, a function generator is connected the ADC VINA and GND as show in the Figure 7.2. The sampling frequency of ADC is initial set to 1 kHz.<br />Oscilloscope+VCOMFunction Generator(DC Offset = 1.65V)<br />Figure 7.2: Sine Wave Signal Measurement Setup<br />Vpp(Fun Gen)Frequency(Fun Gen)VRMS(Volt Meter)Sampling frequencyRemarks0.2V100Hz0.135V1 kHz0.2V10kHz0.111V1 kHzNot accurate due to low sampling frequency0.2V10KHz0.13620 kHz1.0V10kHz0.70420kHz<br />Table 7.2: RMS Sine Wave Voltage Measurement<br />Chapter 8 Conclusion and Recommendation<br />8.1 Conclusion <br />This thesis described the design and validation of a VLSI Test Module implemented on the Spantan3A FPGA system that can be deployed to model a digital voltmeter as long as the signal voltage is within the range of ADC hardware (+0.4V ~ 2.9V). The main problem faced in this project is difficult to understand the hardware initialization and setting within the Spartan-3A board. A lot of effort and time is spend debugging the hardware ADC circuit and LED panel even though the simulation waveform is perfectly working fine in the ModelSIM. Hardware verification result shows that the digital voltmeter using FPGA showed that the result is quite accurate if the sampling frequency is high enough. If the sampling frequency is set to too high, it will capture unwanted noise and as result degrade the performance of the volt meter. Ideally, the sampling frequency will be best to be set around 4~5 time of the signal frequency<br /> <br />8.2 Recommendations for Future Study<br />The input signal for the single channel digital voltmeter is limited to analog DC voltage and sine wave. Future work can also included different types of input signal (square wave, etc) and also enable to read the frequency of the signal. There is also ADC hardware limitation which can only measure the range between 0.4V and 2.9. In order to increase the dynamic voltage range of this digital voltmeter, external circuit can be installed to attenuate the voltage before the Spartan–3A ADC circuit.<br />Critical Review and Reflections<br />Although the general purpose VLSI (Very Large Scale Integration) Test Module based on a FPGA (Field Programmable Gate Array) system attracted much research during the past few decades, the embedded system to model a digital voltmeter research is a new and challenging subject for me. One of the most important parts of the project which is the Literature research, on the overview of Architecture of FPGAs and VHDL programming were carried out first. With the help of project workshop, searching of reference materials were relatively easy. Ngee Ann Polytechnic Library, Lee Kong Chian reference library, IEEE technical papers and World Wide Web were main sources for my literature research. Nevertheless, it is hard to understand most of the research papers initially. After spending more than one month for the literature research, my understanding on the project and technical paper reading skills have improved noticeably. <br />As a second phase, I prepared my project initial report which includes project objectives, investigation of project background, project management, proposed approaches and methods to be employed as well as skills review. As initial planning is important in order to complete the objectives, proposed approaches were systematically analyzed and selected. Project plan was also scheduled with details. <br />Similar to any other students, so many obstacles were encountered while doing the project. The first problem encountered was to understand of the embedded FPGA board (Spartan-3A). Although the Spartan-3A board comes with the instructions and starter kit board user guide, but there is a lot of problem faced when programming the initialization and setting of the hardware. If these setting of the values are not set correct, the program will either not run or hang up.<br />.<br />From this project, we have learnt new skills like drawing a Gantt chart and VHDL programming. Existing skills such as research, analytical, problem solving, project and time management and technical report writing were improved significantly. In short, this project has provided us with terrific chance for learning and improving ourselves technical and critical thinking skills.<br />Bibliography <br />[1] http://en.wikipedia.org/wiki/Field-programmable_gate_array<br />[2] http://en.wikipedia.org/wiki/Voltmeter<br />[3] Clive Lee. IPT Guidance for Acquisition of Systems with Complex Programmable Hardware using DO-254. Jun. (2007). ASSC.<br />[4] Thomas David Vancourt. LAMP: Tools for Creating Application-Specific FPGA Coprocessors. (2006)<br />[5] Stephan Brown and Jonathan Rose, Architecture of FPGAs and CPLDs : A Tutorial, University of Toronto, P7.<br />[6] Xilinx Inc., Spartan-3A FPGA Family: Completer Data Sheet, DS529 March 6, 2009<br />[7] Xilinx Inc., Spartan-3A Starter Kit Board User Guide, UG334 (v1.0) June 19, 2008<br />[8]Introduction to VLSI Design. <br />[9] Kevin Morris, FPGA Simulation: Forget what you learned in ASIC design. FPGA and Programmable Logic Journal. Jun. (2004). <br />[10] Mentor Graphics Inc., URL: http://www.mentor.com/<br />[11] Mentor Graphics Inc., LeonardoSpectrum HDL Synthesis <br />[12] University of Pennsylvania, Introduction to Xilinx ISE 8.2i<br />[13] Xilinx Inc. Xilinx ISE 8 Software Manuals and Help. ISE 8 Manuals.<br />[14] Guillaume Savaton, Jerome Delatour, Karl Courtel. Roll your own Hardware Description Language: An Experiment in Hardware Development using Model Driven Software Tools.<br />APPENDIX: VHDL CODE FOR VOLTMETER<br />----------------------------------------------------------------------------------<br />-- Company: <br />-- Engineer: <br />-- <br />-- Create Date: 10:30:58 08/01/2009 <br />-- Design Name: <br />-- Module Name: voltmeter - Behavioral <br />-- Project Name: <br />-- Target Devices: <br />-- Tool versions: <br />-- Description: <br />--<br />-- Dependencies: <br />--<br />-- Revision: <br />-- Revision 0.01 - File Created<br />-- Additional Comments: <br />--<br />----------------------------------------------------------------------------------<br />library IEEE;<br />use IEEE.STD_LOGIC_1164.ALL;<br />use IEEE.STD_LOGIC_ARITH.ALL;<br />use IEEE.STD_LOGIC_UNSIGNED.ALL;<br />use IEEE.numeric_bit.all;<br />---- Uncomment the following library declaration if instantiating<br />---- any Xilinx primitives in this code.<br />--library UNISIM;<br />--use UNISIM.VComponents.all;<br />entity voltmeter is<br /> Port ( AMP_CS : out STD_LOGIC;<br /> AMP_SHDN : out STD_LOGIC;<br /> CE_AMP : in STD_LOGIC;<br /> CLK : in STD_LOGIC;<br /> CONV : out STD_LOGIC;<br /> LCD : out STD_LOGIC_VECTOR (7 downto 4);<br /> LCD_E : out STD_LOGIC;<br /> LCD_RS : out STD_LOGIC;<br /> LCD_RW : out STD_LOGIC;<br /> START_CONV : in STD_LOGIC;<br /> LED : out STD_LOGIC_VECTOR (7 downto 0);<br /> MOSI : out STD_LOGIC;<br /> PUSH_B : in STD_LOGIC_VECTOR (3 downto 0);<br /> SCK : out STD_LOGIC;<br /> SPI_MISO : in STD_LOGIC;<br /> SW : in STD_LOGIC_VECTOR (3 downto 0);<br /> AMP : in STD_LOGIC);<br />end voltmeter;<br />architecture Behavioral of voltmeter is<br />type state_type is (IDLE, START,START2,HI,HI_DUMMY,LO,LO_DUMMY,FINE,<br /> IDLE_AD, START_AD,HI_AD,LO_AD,FINE_AD,<br /> DECODE1, DECODE2, <br /> BCD_START, BCD_INIT, BCD_ADJ, BCD_SHIFT, BCD_NEXT, BCD_DONE,<br /> PRINT_LCD_START, PRINT_LCD_CODE, PRINT_LCD_DUMMY);<br /> signal next_state, state : state_type; <br />signal counter : integer range 0 to 35 :=0;<br />signal sample : std_logic;<br />signal gain : std_logic_vector(7 downto 0):=xquot;
11quot;
;<br />signal ADC1 : std_logic_vector(13 downto 0):=quot;
00000000000000quot;
;<br />signal ADC2 : std_logic_vector(13 downto 0);<br />signal ADC3 : std_logic_vector(13 downto 0);<br />signal ADC4 : std_logic_vector(13 downto 0);<br />signal sum1 : integer range 0 to 32768:=0;<br />signal sum2 : integer range 0 to 32768:=0;<br />signal sum3 : integer range 0 to 32768:=0;<br />signal sum4 : integer range 0 to 32768:=0;<br />signal sum5 : integer range 0 to 32768:=0;<br />signal sum6 : integer range 0 to 32768:=0;<br />signal sum7: integer range 0 to 32768:=0;<br />signal sum8 : integer range 0 to 32768:=0;<br />signal sum9 : integer range 0 to 32768:=0;<br />signal sum10 : integer range 0 to 32768:=0;<br />signal sum11 : integer range 0 to 32768:=0;<br />signal sum12 : integer range 0 to 32768:=0;<br />signal sum13 : integer range 0 to 32768:=0;<br />signal sum : integer range 0 to 32768:=0;<br />signal total_sum : integer range 0 to 32768:=0;<br />signal result : integer range 0 to 32768:=0;<br />signal result2 : integer range 0 to 32768:=0;<br />signal Vin : std_logic_vector(12 downto 0);<br />signal decoder_on : integer range 0 to 7:=0;<br />signal BCD_on :STD_LOGIC;<br />signal Vin_reg,Vin_shift: std_logic_vector (12 downto 0);<br />signal bcd3_reg, bcd2_reg, bcd1_reg, bcd0_reg: STD_LOGIC_VECTOR (3 downto 0);<br />signal bcd3_adj, bcd2_adj, bcd1_adj, bcd0_adj: STD_LOGIC_VECTOR (3 downto 0);<br />signal bcd3_shift, bcd2_shift, bcd1_shift, bcd0_shift: STD_LOGIC_VECTOR (3 downto 0);<br /> signal bcd3 : STD_LOGIC_VECTOR (3 downto 0);<br /> signal bcd2 : STD_LOGIC_VECTOR (3 downto 0);<br /> signal bcd1 : STD_LOGIC_VECTOR (3 downto 0);<br /> signal bcd0 : STD_LOGIC_VECTOR (3 downto 0);<br /> <br />signal code : STD_LOGIC_VECTOR (3 downto 0);<br /> signal code1 : STD_LOGIC_VECTOR (5 downto 0);<br />signal code2 : STD_LOGIC_VECTOR (5 downto 0);<br />signal int_count : integer range 0 to 49999999 :=0;<br />signal int_count2 : integer range 0 to 49999999 :=0;<br />signal display: integer range 0 to 1:=0;<br />signal clk_display : std_logic_vector(7 downto 0) := quot;
00000000quot;
;<br />signal gain_display : std_logic_vector(7 downto 0) := quot;
00000000quot;
;<br />signal lcd_code: std_logic_vector (5 downto 0); <br />signal text1:std_logic_vector (5 downto 0):=quot;
100011quot;
;<br />signal text2:std_logic_vector (5 downto 0):=quot;
100000quot;
;<br />signal text3:std_logic_vector (5 downto 0):=quot;
100011quot;
;<br />signal text4:std_logic_vector (5 downto 0):=quot;
100000quot;
;<br />signal text5:std_logic_vector (5 downto 0):=quot;
100011quot;
;<br />signal text6:std_logic_vector (5 downto 0):=quot;
100000quot;
;<br />signal text7:std_logic_vector (5 downto 0):=quot;
100011quot;
;<br />signal text8:std_logic_vector (5 downto 0):=quot;
100000quot;
;<br />signal text9:std_logic_vector (5 downto 0):=quot;
100011quot;
;<br />signal text10:std_logic_vector (5 downto 0):=quot;
100000quot;
;<br />signal text11:std_logic_vector (5 downto 0):=quot;
100011quot;
;<br />signal text12:std_logic_vector (5 downto 0):=quot;
100000quot;
;<br /> <br />signal line:std_logic_vector (5 downto 0);<br />--signal text1:std_logic_vector (5 downto 0):=quot;
100101quot;
;<br />--signal text2:std_logic_vector (5 downto 0):=quot;
100011quot;
;<br />-- signal text3:std_logic_vector (5 downto 0):=quot;
100101quot;
;<br />-- signal text4:std_logic_vector (5 downto 0):=quot;
100100quot;
;<br />-- signal text5:std_logic_vector (5 downto 0):=quot;
100100quot;
;<br />-- signal text6:std_logic_vector (5 downto 0):=quot;
100001quot;
;<br />-- signal text7:std_logic_vector (5 downto 0):=quot;
100101quot;
;<br />-- signal text8:std_logic_vector (5 downto 0):=quot;
100010quot;
;<br />-- signal text9:std_logic_vector (5 downto 0):=quot;
100101quot;
;<br />-- signal text10:std_logic_vector (5 downto 0):=quot;
100100quot;
;<br />--signal line:std_logic_vector (5 downto 0):=quot;
001000quot;
;<br />begin<br />process(START_CONV,CE_AMP,state,counter)<br />variable bit_count : integer range 0 to 15;<br />variable BCD_bit_count : integer range 0 to 15;<br />variable LCD_char_count : integer range 0 to 15;<br />begin<br />case state is<br />when IDLE =><br />if CE_AMP ='1' then<br />next_state <= START;<br />else<br />next_state <= IDLE;<br />end if;<br />when START =><br />next_state <= START2;<br />bit_count :=0;<br />when START2 =><br />next_state <= HI;<br />when HI =><br />if counter = 2 then<br />next_state <= HI_DUMMY;<br />else<br />next_state <= HI;<br />end if;<br />when HI_DUMMY =><br />bit_count := bit_count + 1;<br />next_state <= LO;<br />when LO =><br />if counter = 2 then<br />next_state <= LO_DUMMY;<br />else<br />next_state <= LO;<br />end if;<br />when LO_DUMMY =><br />if bit_count = 8 then<br />next_state <= FINE;<br />else<br />next_state <= HI;<br />end if;<br />when FINE =><br />next_state <= IDLE_AD;<br />when IDLE_AD =><br />if start_conv ='1' then<br />next_state <= START_AD;<br />else<br />next_state <= IDLE_AD;<br />end if;<br />when START_AD =><br />next_state <= HI_AD;<br />when HI_AD =><br />next_state <= LO_AD;<br />when LO_AD =><br />if counter = 34 then<br />next_state <= FINE_AD;<br />else<br />next_state <= HI_AD;<br />end if;<br />when FINE_AD =><br />next_state <= DECODE1;<br />when DECODE1 =><br />next_state <= DECODE2;<br />when DECODE2 =><br />next_state <= BCD_START;<br />when BCD_START =><br />next_state <= BCD_INIT;<br />BCD_bit_count:=0;<br />when BCD_INIT =><br />next_state <= BCD_ADJ;<br />when BCD_ADJ=><br />next_state <= BCD_SHIFT;<br />when BCD_SHIFT =><br />next_state <= BCD_NEXT;<br />when BCD_NEXT =><br />if BCD_bit_count=12 then<br />next_state <= BCD_DONE;<br />else<br />BCD_bit_count:=BCD_bit_count+1;<br />next_state <= BCD_ADJ;<br />end if;<br />when BCD_DONE =><br />next_state <= PRINT_LCD_START;<br />LCD_char_count:=0;<br />when PRINT_LCD_START =><br />next_state <= PRINT_LCD_CODE;<br />when PRINT_LCD_CODE =><br />if LCD_char_count=4 then<br />next_state <= IDLE_AD;<br />else<br />LCD_char_count:=LCD_char_count+1;<br />next_state <= PRINT_LCD_DUMMY;<br />end if;<br />when PRINT_LCD_DUMMY =><br />next_state <= PRINT_LCD_START;<br />when others =><br />next_state <= IDLE_AD; <br />end case;<br />end process;<br />process (CLK)<br /> variable count: std_logic_vector(26 downto 0) :=quot;
000000000000000000000000000quot;
;<br /> variable initialise : integer range 0 to 1:=0;<br /> <br /> begin<br /> if (CLK'event and CLK='1') then <br /> count := count + 1;<br /> --sf_ce0 <= '1'; <br /> case (count(26 downto 21)) is<br /> when quot;
000000quot;
=> lcd_code <= quot;
000011quot;
; -- power-on initialization<br /> when quot;
000001quot;
=> lcd_code <= quot;
000011quot;
;<br /> when quot;
000010quot;
=> lcd_code <= quot;
000011quot;
;<br /> when quot;
000011quot;
=> lcd_code <= quot;
000010quot;
;<br /> when quot;
000100quot;
=> lcd_code <= quot;
000010quot;
; -- function set<br /> when quot;
000101quot;
=> lcd_code <= quot;
001000quot;
;<br /> when quot;
000110quot;
=> lcd_code <= quot;
000000quot;
; -- entry mode set<br /> when quot;
000111quot;
=> lcd_code <= quot;
000110quot;
;<br /> when quot;
001000quot;
=> lcd_code <= quot;
000000quot;
; -- display on/off control<br /> when quot;
001001quot;
=> lcd_code <= quot;
001100quot;
;<br /> when quot;
001010quot;
=> lcd_code <= quot;
000000quot;
; -- display clear<br /> when quot;
001011quot;
=> lcd_code <= quot;
000001quot;
;<br /> when quot;
001100quot;
=> lcd_code <= quot;
100101quot;
; -- R 100101 100010<br /> when quot;
001101quot;
=> lcd_code <= quot;
100010quot;
;-- <br /> <br /> when quot;
001110quot;
=> lcd_code <= quot;
100100quot;
; -- M 100100 101101<br /> when quot;
001111quot;
=> lcd_code <= quot;
101101quot;
;-- <br /> <br /> when quot;
010000quot;
=> lcd_code <= quot;
100101quot;
; -- S 100101 100011<br /> when quot;
010001quot;
=> lcd_code <= quot;
100011quot;
;-- <br /> <br /> --when quot;
010010quot;
=> lcd_code <= quot;
001100quot;
; -- Set DD RAM address to 40<br /> --when quot;
010011quot;
=> lcd_code <= quot;
000000quot;
;-- <br /> <br /> when quot;
010100quot;
=> lcd_code <= quot;
100101quot;
; -- V 100101 100110<br /> when quot;
010101quot;
=> lcd_code <= quot;
100110quot;
;-- <br /> <br /> when quot;
010110quot;
=> lcd_code <= quot;
100110quot;
; -- o 100110 101111<br /> when quot;
010111quot;
=> lcd_code <= quot;
101111quot;
;-- <br /> <br /> when quot;
011000quot;
=> lcd_code <= quot;
100110quot;
; -- l 100110 101100<br /> when quot;
011001quot;
=> lcd_code <= quot;
101100quot;
;-- <br /> when quot;
011010quot;
=> lcd_code <= quot;
100111quot;
; -- t 100111 100100<br /> when quot;
011011quot;
=> lcd_code <= quot;
100100quot;
;-- <br /> when quot;
011100quot;
=> lcd_code <= quot;
100110quot;
; -- a 100110 100001<br /> when quot;
011101quot;
=> lcd_code <= quot;
100001quot;
;-- <br /> when quot;
011110quot;
=> lcd_code <= quot;
100110quot;
; -- g 100110 100111<br /> when quot;
011111quot;
=> lcd_code <= quot;
100111quot;
;-- <br /> when quot;
100000quot;
=> lcd_code <= quot;
100110quot;
; -- e 100110 100101<br /> when quot;
100001quot;
=> lcd_code <= quot;
100101quot;
;-- <br /> when quot;
100010quot;
=> lcd_code <= quot;
001100quot;
; -- Set DD RAM address to 40<br /> when quot;
100011quot;
=> lcd_code <= quot;
000000quot;
;-- <br /> when quot;
100100quot;
=> lcd_code <= text1; -- R 100101 100010<br /> when quot;
100101quot;
=> lcd_code <= text2; -- <br /> <br /> when quot;
100110quot;
=> lcd_code <= text3; -- M 100100 101101<br /> when quot;
100111quot;
=> lcd_code <= text4; -- <br /> <br /> when quot;
101000quot;
=> lcd_code <= quot;
101010quot;
; -- S 100101 100011<br /> when quot;
101001quot;
=> lcd_code <= quot;
100101quot;
; -- <br /> <br /> when quot;
101010quot;
=> lcd_code <= text7; -- Set DD RAM address to 40<br /> when quot;
101011quot;
=> lcd_code <= text8; -- <br /> <br /> when quot;
101100quot;
=> lcd_code <= text9; -- V 100101 100110<br /> when quot;
101101quot;
=> lcd_code <= text10; -- <br /> <br /> when quot;
101110quot;
=> lcd_code <= quot;
001100quot;
; -- Set DD RAM address to 40<br /> when quot;
101111quot;
=> lcd_code <= quot;
001001quot;
;-- <br /> when quot;
110000quot;
=> lcd_code <= text11; -- V 100101 100110<br /> when quot;
110001quot;
=> lcd_code <= text12; -- <br /> <br /> when others => lcd_code <= quot;
010000quot;
;<br /> end case;<br /> <br /> <br /> end if;<br /> <br /> LCD_E <= (count(20) xor count(19)) and (not lcd_code(4)); --divide the clock rate by 2^21<br /> LCD_RS <= lcd_code(5);<br /> LCD_RW <= lcd_code(4);<br /> LCD(7) <= lcd_code(3);<br /> LCD(6) <= lcd_code(2);<br /> LCD(5) <= lcd_code(1);<br /> LCD(4) <= lcd_code(0);<br /> <br /> end process ;<br />process(CLK)<br />begin<br />if decoder_on=0 then<br />if CLK'event and CLK ='1' then<br />state <= next_state;<br />end if;<br />sum<=0;sum1<=0;sum2<=0;sum3<=0;sum4<=0;sum5<=0;sum6<=0;sum7<=0;sum8<=0;sum9<=0;sum10<=0;sum11<=0;sum12<=0;sum13<=0;<br />else<br />if ADC1(13)='1' then<br />ADC3 <= ADC1 XOR quot;
11111111111111quot;
;<br />ADC4 <= ADC3 +1;<br />ADC4(13)<='0'; <br />else<br />ADC4 <= ADC1;<br />end if;<br />if ADC4(0)='1' then sum1<=1; end if;<br />if ADC4(1)='1' then sum2<= 2; end if;<br />if ADC4(2)='1' then sum3<= 4; end if;<br />if ADC4(3)='1' then sum4<= 8; end if;<br />if ADC4(4)='1' then sum5<= 16; end if;<br />if ADC4(5)='1' then sum6<= 32; end if;<br />if ADC4(6)='1' then sum7<= 64; end if;<br />if ADC4(7)='1' then sum8<= 128; end if;<br />if ADC4(8)='1' then sum9<= 256; end if;<br />if ADC4(9)='1' then sum10<=512; end if;<br />if ADC4(10)='1' then sum11<=1024; end if;<br />if ADC4(11)='1' then sum12<=2048; end if;<br />if ADC4(12)='1' then sum13<=4096; end if;<br />total_sum<=sum1+sum2+sum3+sum4+sum5+sum6+sum7+sum8+sum9+sum10+sum11+sum12+sum13;<br />end if;<br />end process;<br />process (CLK)<br />variable index1 : integer range 0 to 15;<br />variable index2 : integer range 0 to 15;<br />variable print_char_no : integer range 0 to 7;<br />variable gain_count : integer range 0 to 7;<br />begin <br />AMP_SHDN <= '0';<br />if CLK'event and CLK ='1' then<br />case state is <br />when IDLE =><br />SCK <= '0';<br />AMP_CS <= '1';<br />MOSI <='0';<br />counter <=0;<br />gain_count:=0;<br />LED<=Xquot;
00quot;
;<br />text11<=quot;
100100quot;
;<br />text12<=quot;
100001quot;
;<br />when START =><br />AMP_CS <= '0';<br />index1 := 7; -- 8 bit value<br />LED<=Xquot;
01quot;
;<br />when START2 =><br />MOSI <= gain(index1);<br />LED<=Xquot;
02quot;
;<br />when HI =><br /> <br />SCK <= '1';<br />counter <= counter +1;<br />LED<=Xquot;
03quot;
;<br />when HI_DUMMY =><br />counter <=0;<br />LED<=Xquot;
04quot;
;<br />when LO =><br />SCK <= '0';<br />counter <= counter +1;<br />LED<=Xquot;
05quot;
;<br />when LO_DUMMY =><br />MOSI <= gain(index1);<br />LED<=Xquot;
06quot;
;<br />index1 := index1-1;<br />counter <=0;<br />when FINE =><br />AMP_CS <='1';<br />SCK <= '0';<br />MOSI <= '0';<br />LED<=Xquot;
07quot;
;<br />text11<=quot;
100100quot;
;<br />text12<=quot;
100010quot;
;<br />when IDLE_AD =><br />SCK <= '0';<br />CONV <= '0';<br />sample <='0';<br />LED<=Xquot;
08quot;
;<br />text11<=quot;
100100quot;
;<br />text12<=quot;
100010quot;
;<br />when START_AD =><br />SCK <= '0';<br />CONV <= '1';<br />counter <= 0;<br />sample <='0';<br />index1 := 13; -- 14 bit value<br />index2 := 13; -- 14 bit value<br />LED<=Xquot;
09quot;
;<br />when HI_AD =><br />SCK <= '1';<br />CONV <= '0';<br />counter <= counter +1;<br />sample <='0';<br />LED<=Xquot;
0Aquot;
;<br />when LO_AD =><br />SCK <= '0';<br />CONV <= '0';<br />LED<=Xquot;
0Bquot;
;<br />if(counter >2 and counter < 17) then<br />--if index1 = 13 then<br />--ADC1(index1) <= not SPI_MISO;<br />--else<br />ADC1(index1) <= SPI_MISO;<br />--end if;<br />index1 := index1 -1;<br />sample <='1';<br />elsif(counter > 18 and counter < 33) then<br />--if index2 = 13 then<br />--ADC2(index2) <= not SPI_MISO;<br />--else<br />ADC2(index2) <= SPI_MISO;<br />--end if;<br />index2 := index2 -1;<br />sample <='1';<br />else<br />sample <='0';<br />end if;<br />when FINE_AD =><br />counter <= 0;<br />sample <='0';<br />SCK <= '0';<br />CONV <= '0';<br />LED<=Xquot;
0Cquot;
;<br />decoder_on<=1;<br />when DECODE1 =><br />SCK <= '0';<br />CONV <= '0';<br />AMP_CS <= '1';<br />MOSI <='0';<br />LED<=Xquot;
0Dquot;
;<br />decoder_on<=0;<br />text11<=quot;
100100quot;
;<br />text12<=quot;
100011quot;
;<br />when DECODE2 =><br />SCK <= '0';<br />CONV <= '0';<br />AMP_CS <= '1';<br />MOSI <='0';<br />LED<=Xquot;
0Equot;
;<br />if ADC1(13)='1' then<br />result2 <= total_sum*125/8192 +125;<br />else<br />result2 <=125-total_sum*125/8192 ;<br />end if;<br />when BCD_START =><br />SCK <= '0';<br />CONV <= '0';<br />AMP_CS <= '1';<br />MOSI <='0';<br />LED<=Xquot;
0Fquot;
;<br />Vin <=conv_std_logic_vector(result2,13);<br />BCD_on <= '1';<br />when BCD_INIT =><br />SCK <= '0';<br />CONV <= '0';<br />AMP_CS <= '1';<br />MOSI <='0';<br />LED<=Xquot;
10quot;
;<br />BCD_on <= '1';<br />Vin_reg <=Vin;<br />bcd3_reg<=(others =>'0');<br />bcd2_reg<=(others =>'0');<br />bcd1_reg<=(others =>'0');<br />bcd0_reg<=(others =>'0');<br />when BCD_ADJ =><br />SCK <= '0';<br />CONV <= '0';<br />AMP_CS <= '1';<br />MOSI <='0';<br />LED<=Xquot;
12quot;
;<br />BCD_on <= '1';<br />if bcd0_reg > 4 then<br />bcd0_adj <=bcd0_reg+3;<br />else<br />bcd0_adj <= bcd0_reg;<br />end if;<br />if bcd1_reg > 4 then<br />bcd1_adj <=bcd1_reg+3;<br />else<br />bcd1_adj <= bcd1_reg;<br />end if;<br />if bcd2_reg > 4 then<br />bcd2_adj <=bcd2_reg+3;<br />else<br />bcd2_adj <= bcd2_reg;<br />end if;<br />if bcd3_reg > 4 then<br />bcd3_adj <=bcd3_reg+3;<br />else<br />bcd3_adj <= bcd3_reg;<br />end if;<br />when BCD_SHIFT =><br />SCK <= '0';<br />CONV <= '0';<br />AMP_CS <= '1';<br />MOSI <='0';<br />LED<=Xquot;
13quot;
;<br />BCD_on <= '1';<br />Vin_shift <= Vin_reg(11 downto 0) & '0';<br />bcd0_shift <= bcd0_adj(2 downto 0) & Vin_reg(12);<br />bcd1_shift <= bcd1_adj(2 downto 0) & bcd0_adj(3);<br />bcd2_shift <= bcd2_adj(2 downto 0) & bcd1_adj(3);<br />bcd3_shift <= bcd3_adj(2 downto 0) & bcd2_adj(3);<br />when BCD_NEXT =><br />SCK <= '0';<br />CONV <= '0';<br />AMP_CS <= '1';<br />MOSI <='0';<br />LED<=Xquot;
14quot;
;<br />BCD_on <= '1';<br /> <br />Vin_reg <= Vin_shift;<br />bcd0_reg <=bcd0_shift;<br />bcd1_reg <=bcd1_shift;<br />bcd2_reg <=bcd2_shift;<br />bcd3_reg <=bcd3_shift;<br />when BCD_DONE =><br />SCK <= '0';<br />CONV <= '0';<br />AMP_CS <= '1';<br />MOSI <='0';<br />LED<=Xquot;
15quot;
;<br />BCD_on <= '0';<br />bcd0 <= std_logic_vector (bcd0_reg);<br />bcd1 <= std_logic_vector (bcd1_reg);<br />bcd2 <= std_logic_vector (bcd2_reg);<br />bcd3 <= std_logic_vector (bcd3_reg);<br />print_char_no:=0;<br />when PRINT_LCD_START =><br />SCK <= '0';<br />CONV <= '0';<br />AMP_CS <= '1';<br />MOSI <='0';<br />LED<=Xquot;
16quot;
;<br /> if print_char_no=0 then <br />code<= bcd0;<br />elsif print_char_no=1 then <br />code<= bcd1;<br />elsif print_char_no=2 then<br />code<= bcd2;<br />else<br />code<= bcd3;<br />end if;<br />text11<=quot;
100100quot;
;<br />text12<=quot;
100100quot;
;<br />when PRINT_LCD_CODE =><br />case code is <br />when quot;
0000quot;
=> code1 <= quot;
100011quot;
; code2 <= quot;
100000quot;
;<br />when quot;
0001quot;
=> code1 <= quot;
100011quot;
; code2 <= quot;
100001quot;
;<br />when quot;
0010quot;
=> code1 <= quot;
100011quot;
; code2 <= quot;
100010quot;
;<br />when quot;
0011quot;
=> code1 <= quot;
100011quot;
; code2 <= quot;
100011quot;
;<br />when quot;
0100quot;
=> code1 <= quot;
100011quot;
; code2 <= quot;
100100quot;
;<br />when quot;
0101quot;
=> code1 <= quot;
100011quot;
; code2 <= quot;
100101quot;
;<br />when quot;
0110quot;
=> code1 <= quot;
100011quot;
; code2 <= quot;
100110quot;
;<br />when quot;
0111quot;
=> code1 <= quot;
100011quot;
; code2 <= quot;
100111quot;
;<br />when quot;
1000quot;
=> code1 <= quot;
100011quot;
; code2 <= quot;
101000quot;
;<br />when quot;
1001quot;
=> code1 <= quot;
100011quot;
; code2 <= quot;
101001quot;
;<br />when others => code1 <= quot;
100010quot;
; code2 <= quot;
100011quot;
;<br />end case;<br />when PRINT_LCD_DUMMY =><br />if print_char_no=0 then <br />text9<= code1;<br />text10<= code2;<br />elsif print_char_no=1 then <br />text7<= code1;<br />text8<= code2;<br />elsif print_char_no=2 then<br />text3<= code1;<br />text4<= code2;<br />else<br />text1<= code1;<br />text2<= code2;<br />end if;<br />print_char_no:=print_char_no+1;<br />LED<=Xquot;
FFquot;
;<br />when others =><br />SCK <= '0';<br />CONV <= '0';<br />AMP_CS <= '1';<br />MOSI <='0';<br />LED<=Xquot;
00quot;
;<br />end case;<br />end if;<br />end process;<br />end Behavioral;<br />Glossary<br />AC<br />In alternating current (AC, also ac) the movement (or flow) of electric charge periodically reverses direction. An electric charge would for instance move forward, then backward, then forward, then backward, over and over again<br />BCD<br />In computing and electronic systems, binary-coded decimal (BCD) (sometimes called natural binary-coded decimal, NBCD) is an encoding for decimal numbers in which each digit is represented by its own binary sequence<br />DC<br />In direct current (DC), the movement (or flow) of electric charge is only in one direction.<br />Flowchart<br />A flowchart is a common type of diagram that represents an algorithm or process showing the steps as boxes of various kinds, and their order by connecting these with arrows. Flowcharts are used in analyzing, designing, documenting or managing a process or program in various fields<br />FPGA<br />FPGAs contain programmable logic components called quot;
logic blocksquot;
, and a hierarchy of reconfigurable interconnects that allow the blocks to be quot;
wired togetherquot;
—somewhat like a one-chip programmable breadboard. Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory<br />HDL<br />In electronics, a hardware description language or HDL is any language from a class of computer languages and/or programming languages for formal description of electronic circuits, and more specifically, digital logic. It can describe the circuit's operation, its design and organization, and tests to verify its operation by means of simulation<br />LCD<br />A liquid crystal display (LCD) is a thin, flat panel used for electronically displaying information such as text, images, and moving pictures.<br />Sampling Frequency<br />The sampling rate, sample rate, or sampling frequency defines the number of samples per second (or per other unit) taken from a continuous signal to make a discrete signal. For time-domain signals, it can be measured in samples per second (S/s),[1] or hertz (Hz).[2] The inverse of the sampling frequency is the sampling period or sampling interval, which is the time between samples<br />RMS<br />The RMS value of a set of values (or a continuous-time waveform) is the square root of the arithmetic mean (average) of the squares of the original values (or the square of the function that defines the continuous waveform).<br />VLSI<br />Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistor-based circuits into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed<br />End of Report<br />