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Session eight

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http://www.bized.co.uk Session 8 Prepared by Alaa Salah Shehata Mahmoud A. M. Abd El Latif Mohamed Mohamed Tala’t Mohamed Salah Mahmoud Version 02 – October 2011 Copyright 2006 – Biz/ed
http://www.bized.co.uk - Evaluation Test 8 - Arithmetic Circuits Contents - Tutorial [2] - IP Cores - ISIM Simulator - Language Templates - VHDL Coding TIPS 2 Copyright 2006 – Biz/ed
http://www.bized.co.uk Evaluation Test Answer all questions in the following paper Questions : 50 Question Time : 30 minute Full Mark : 100 degree Copyright 2006 – Biz/ed
Evaluation Test http://www.bized.co.uk Question Choice 1 A 2 B 3 -- 4 -- 5 6 7 8 Answer all questions in the paper 9 10 11 12 13 14 15 16 17 18 19 20 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk Arithmetic Circuits 5 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk Unsigned and Signed Types Definition Behave exactly like STD_LOGIC_VECTOR They determine whether a given vector should be treated as a signed or unsigned number. Package ieee.numeric_std.all Unsigned 0 to 2N - 1 Signed - 2(N-1) to 2(N-1) – 1 2's Complement number Example signal A : unsigned(3 downto 0) ; signal B : signed(3 downto 0) ; A <= "1111" ; -- 15 B <= "1111" ; -- -1 6 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk Ambiguous Expressions Ambiguous Z_signed <= A_signed + "1010"; Error -6 or 10 Solution Z_signed <= A_signed + signed("1010“); 7 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk Adders with Carry In Result A(3:0) + B(3:0) + Carry-In Algorithm A(3:0) , ‘1’ 011 1 011 1 B(3:0) , Carry-In 001 1 001 0 -------------------- ------- cin =1 ------- cin =0 Result(4:1) 101 0 100 0 Code Signal A,B,Y : unsigned (3 downto 0); Signal Z : unsigned (4 downto 0); Signal cin : std_logic; Z <= (A & ’1’) + (B & cin); Y <= Z(4 downto 1 ); 8 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk Adders with Carry Out Result Result + Carry-Out Algorithm ‘0’ A(3:0) 0 111 ‘0’ B(3:0) 0 100 --------------------- ------- Cout Result(3:0) 1 011 Code Signal A,B,Y : unsigned (3 downto 0); Signal Z : unsigned (4 downto 0); Signal co : std_logic; Z <= (’0’ & A) + (’0’ & B); Y <= Z(3 downto 0 ); Co <= Y(4); 9 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk Type Conversions Conversions Signed & Unsigned (elements)  Std_Logic Signed & Unsigned  Std_Logic_Vector Signed & Unsigned  Integer Std_Logic_vector  Integer Conversion functions located in Numeric_Std 10 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk Unsigned.Signed  Std_Logic Conversions Converted automatically. Example A_std <= J_unsigned(0); B_std <= K_signed(7); --to std_ulogic not preferred L_unsigned(0) <= C_std; M_signed(2) <= N_std(2); 11 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk Unsigned.Signed  Std_Logic_vector Conversions Use type casting to convert equal sized arrays Example A_std <= std_logic_vector( B_unsigned ) ; C_std <= std_logic_vector( D_signed ) ; G_unsigned <= unsigned( H_std ) ; J_signed <= signed( K_std ) ; 12 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk Unsigned.Signed  Integer Conversions Use conversion functions Example Signal A,B : integer; Signal A_unsigned : unsigned(7 downto 0); Signal B_signed : signed(7 downto 0); A <= TO_INTEGER ( A_unsigned ) ; B <= TO_INTEGER ( B_signed ) ; A_unsigned <= TO_UNSIGNED ( A, 8) ; B_signed <= TO_SIGNED ( B, 8) ; Data <= ROM(( TO_INTEGER( Addr_uv)); 13 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk Std_logic_vector  Integer Conversions Use conversion functions + type casting i.e. Needs 2 steps. Example Signal A,B : integer; Signal A_std : std_logic_vector (7 downto 0); Signal B_std : std_logic_vector (7 downto 0); A <= to_integer( unsigned( A_std )); B <= to_integer( signed( B_std )); A_std <= std_logic_vector( to_unsigned( A, 8 )); B_std <= std_logic_vector( to_signed( B, 8 )); 14 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk Multiplication and Division Operators * / mod rem ** Signal * Constant Z_unsigned <= A_unsigned * 2 ; Size of result = 2 * size of input signal Signal* Signal Signal A_unsigned : unsigned (7 downto 0); Signal B_unsigned : unsigned (7 downto 0); Signal Z_unsigned : unsigned (15 downto 0); Z_unsigned <= A_unsigned * B_unsigned ; Size of result = size of 1st signal + size of 2nd signal Synthesis / mod rem are not synthesis 15 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk VHDL is Strongly typed <= Less Errors ; Strong Typing  Strong Error Checking Built into the Compiler less debugging. 16 Without VHDL, you must have a good Testbench+ lots of time to catch your errors. Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk • Signed Adder Example 35 17 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.numeric_std.all ; --------------------------------------- ENTITY adder IS PORT ( Cin : IN STD_LOGIC ; X,Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0); S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); END adder ; --------------------------------------- ARCHITECTURE Behavior OF adder IS SIGNAL Xs,Ys : SIGNED(15 DOWNTO 0); SIGNAL Sum : SIGNED(15 DOWNTO 0); BEGIN Xs <= signed(X); Ys <= signed(Y); Sum <= Xs + Ys + Cin ; S <= std_logic_vector(Sum); END Behavior ; 18 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_signed.all ; --------------------------------------- ENTITY adder IS PORT ( Cin : IN STD_LOGIC ; X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)) ; END adder ; --------------------------------------- ARCHITECTURE Behavior OF adder IS BEGIN S <= X + Y + Cin ; END Behavior ; Not Recommended 19 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk ENTITY adder16 IS PORT (X,Y: IN INTEGER RANGE -32768 TO 32767 ; S : OUT INTEGER RANGE -32768 TO 32767 ) ; END adder16 ; --------------------------------------- ARCHITECTURE Behavior OF adder16 IS BEGIN S <= X + Y ; END Behavior ; Not Recommended 20 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk • UnSigned Adder Example 35 21 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.numeric_std.all ; --------------------------------------- ENTITY adder16 IS PORT ( Cin : IN STD_LOGIC ; X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)) ; END adder16 ; --------------------------------------- ARCHITECTURE Behavior OF adder16 IS SIGNAL Xus : UNSIGNED(15 DOWNTO 0); SIGNAL Yus : UNSIGNED(15 DOWNTO 0); SIGNAL Sum : UNSIGNED(15 DOWNTO 0); BEGIN Xus <= unsigned(X); Yus <= unsigned(Y); Sum <= Xus + Yus + Cin ; S <= std_logic_vector(Sum) ; END Behavior ; 22 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; --------------------------------------- ENTITY adder16 IS PORT ( Cin : IN STD_LOGIC ; X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)) ; END adder16 ; --------------------------------------- ARCHITECTURE Behavior OF adder16 IS SIGNAL Sum : STD_LOGIC_VECTOR(16 DOWNTO 0) ; BEGIN S <= X + Y + Cin ; END Behavior ; Not Recommended 23 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk • Multiplier Example 36 24 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all ; --------------------------------------- begin entity multiply is port( -- signed multiplication a : in STD_LOGIC_VECTOR(7 downto 0); sa <= SIGNED(a); b : in STD_LOGIC_VECTOR(7 downto 0); sb <= SIGNED(b); cu : out STD_LOGIC_VECTOR(15 downto 0); sc <= sa * sb; cs : out STD_LOGIC_VECTOR(15 downto 0)); cs <= STD_LOGIC_VECTOR(sc); end multiply; --------------------------------------- -- unsigned multiplication architecture rtl of multiply is ua <= UNSIGNED(a); ub <= UNSIGNED(b); SIGNAL sa: SIGNED(7 downto 0); uc <= ua * ub; SIGNAL sb: SIGNED(7 downto 0); cu <= STD_LOGIC_VECTOR(uc); SIGNAL sc: SIGNED(15 downto 0); end rtl; SIGNAL ua: UNSIGNED(7 downto 0); SIGNAL ub: UNSIGNED(7 downto 0); SIGNAL uc: UNSIGNED(15 downto 0); 25 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk • Half Adder Example 37 26 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; --------------------------------------- ENTITY HALF_ADDER IS Generic (WIDTH : INTEGER := 8 ); PORT( A : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0 ); B : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0 ); P : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0 ); G : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0 )); END HALF_ADDER; --------------------------------------- ARCHITECTURE RTL OF HALF_ADDER IS BEGIN P <= A XOR B; G <= A AND B; END; 27 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk • Full Adder Example 38 28 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk LIBRARY ieee; USE ieee.std_logic_1164.all; --------------------------------------- ENTITY fullAdder IS PORT( In1, In2, CarryIn : IN std_logic; Sum : OUT std_logic; CarryOut : OUT std_logic); END fullAdder; --------------------------------------- ARCHITECTURE expr OF fullAdder IS signal temp : std_logic; BEGIN temp <= In1 XOR In2; Sum <= temp XOR CarryIn; CarryOut <= (In1 AND In2) OR (CarryIn AND temp); END expr; 29 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk Describe code performing this function C = A + B*2 A,B and C are of width = 16 signed bits C = B*A A,B and C are of width = 16 signed bits lab 15 30 Copyright 2006 – Biz/ed
http://www.bized.co.uk Next Part is inside Start Group tutorial [2] Start Group tutorial [2] Prepared by Alaa Salah Shehata Mahmoud A. M. Abd El Latif Mohamed Mohamed Tala’t Mohamed Salah Mahmoud Version 02 – October 2011 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk 32 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk Design First Data, then Controller Keep it Simple and Stupid (KISS) -VHDL coding is not a -The world’s greatest FSM substitute for design. won’t solve your problems -The best data block is a -Draw a block diagram of in your data blocks. dumb one. your data path using -Make sure your data -Put all of the intelligence familiar building blocks blocks supports your into the controller, where it from digital logic. algorithm. belongs. -Make certain it will work. You can fake FSM signals during simulation while you get your data blocks working. 33 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk Code What You Know Generic Your Code Reduce Simulation Time - If you don’t know how a - Generic Codes are easier construct will synthesize, in reading and modifying. - Simulation is a way to don’t use it. debug a design. -If you can’t draw it, you -The more time you spend can’t code it. up front thinking about your design and how it should behave, the less time you will spend simulating. 34 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk Avoid Synthesizing Non-Clocked Process Entity Interface Unwanted Latches Latches -USE only In and OUT -FSM output process - All Signals in a non- modes. should define a value for clocked process should be -USE only std_logic and all output signals. in the sensitivity list . std_logic_vectors. -Recommended : Register -Don’t use concurrent - Assign a default value for your output. statements to store all signals. values. 35 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk Comments -Don’t think that I can understand all what you say through your code. -Help me with a lot of comments !! And Finally write the Tips you notice when writing your first codes. You will repeat your errors a lot but this way may help you reducing this time. 36 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk Questions Session-8 37 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk Take Your Notes Print the slides and take your notes here --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- 38 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk Take Your Notes Print the slides and take your notes here --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- 39 Copyright 2006 – Biz/ed
Session 8 http://www.bized.co.uk See You Next Session 40 Copyright 2006 – Biz/ed

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Session eight

  • 1. http://www.bized.co.uk Session 8 Prepared by Alaa Salah Shehata Mahmoud A. M. Abd El Latif Mohamed Mohamed Tala’t Mohamed Salah Mahmoud Version 02 – October 2011 Copyright 2006 – Biz/ed
  • 2. http://www.bized.co.uk - Evaluation Test 8 - Arithmetic Circuits Contents - Tutorial [2] - IP Cores - ISIM Simulator - Language Templates - VHDL Coding TIPS 2 Copyright 2006 – Biz/ed
  • 3. http://www.bized.co.uk Evaluation Test Answer all questions in the following paper Questions : 50 Question Time : 30 minute Full Mark : 100 degree Copyright 2006 – Biz/ed
  • 4. Evaluation Test http://www.bized.co.uk Question Choice 1 A 2 B 3 -- 4 -- 5 6 7 8 Answer all questions in the paper 9 10 11 12 13 14 15 16 17 18 19 20 Copyright 2006 – Biz/ed
  • 5. Session 8 http://www.bized.co.uk Arithmetic Circuits 5 Copyright 2006 – Biz/ed
  • 6. Session 8 http://www.bized.co.uk Unsigned and Signed Types Definition Behave exactly like STD_LOGIC_VECTOR They determine whether a given vector should be treated as a signed or unsigned number. Package ieee.numeric_std.all Unsigned 0 to 2N - 1 Signed - 2(N-1) to 2(N-1) – 1 2's Complement number Example signal A : unsigned(3 downto 0) ; signal B : signed(3 downto 0) ; A <= "1111" ; -- 15 B <= "1111" ; -- -1 6 Copyright 2006 – Biz/ed
  • 7. Session 8 http://www.bized.co.uk Ambiguous Expressions Ambiguous Z_signed <= A_signed + "1010"; Error -6 or 10 Solution Z_signed <= A_signed + signed("1010“); 7 Copyright 2006 – Biz/ed
  • 8. Session 8 http://www.bized.co.uk Adders with Carry In Result A(3:0) + B(3:0) + Carry-In Algorithm A(3:0) , ‘1’ 011 1 011 1 B(3:0) , Carry-In 001 1 001 0 -------------------- ------- cin =1 ------- cin =0 Result(4:1) 101 0 100 0 Code Signal A,B,Y : unsigned (3 downto 0); Signal Z : unsigned (4 downto 0); Signal cin : std_logic; Z <= (A & ’1’) + (B & cin); Y <= Z(4 downto 1 ); 8 Copyright 2006 – Biz/ed
  • 9. Session 8 http://www.bized.co.uk Adders with Carry Out Result Result + Carry-Out Algorithm ‘0’ A(3:0) 0 111 ‘0’ B(3:0) 0 100 --------------------- ------- Cout Result(3:0) 1 011 Code Signal A,B,Y : unsigned (3 downto 0); Signal Z : unsigned (4 downto 0); Signal co : std_logic; Z <= (’0’ & A) + (’0’ & B); Y <= Z(3 downto 0 ); Co <= Y(4); 9 Copyright 2006 – Biz/ed
  • 10. Session 8 http://www.bized.co.uk Type Conversions Conversions Signed & Unsigned (elements)  Std_Logic Signed & Unsigned  Std_Logic_Vector Signed & Unsigned  Integer Std_Logic_vector  Integer Conversion functions located in Numeric_Std 10 Copyright 2006 – Biz/ed
  • 11. Session 8 http://www.bized.co.uk Unsigned.Signed  Std_Logic Conversions Converted automatically. Example A_std <= J_unsigned(0); B_std <= K_signed(7); --to std_ulogic not preferred L_unsigned(0) <= C_std; M_signed(2) <= N_std(2); 11 Copyright 2006 – Biz/ed
  • 12. Session 8 http://www.bized.co.uk Unsigned.Signed  Std_Logic_vector Conversions Use type casting to convert equal sized arrays Example A_std <= std_logic_vector( B_unsigned ) ; C_std <= std_logic_vector( D_signed ) ; G_unsigned <= unsigned( H_std ) ; J_signed <= signed( K_std ) ; 12 Copyright 2006 – Biz/ed
  • 13. Session 8 http://www.bized.co.uk Unsigned.Signed  Integer Conversions Use conversion functions Example Signal A,B : integer; Signal A_unsigned : unsigned(7 downto 0); Signal B_signed : signed(7 downto 0); A <= TO_INTEGER ( A_unsigned ) ; B <= TO_INTEGER ( B_signed ) ; A_unsigned <= TO_UNSIGNED ( A, 8) ; B_signed <= TO_SIGNED ( B, 8) ; Data <= ROM(( TO_INTEGER( Addr_uv)); 13 Copyright 2006 – Biz/ed
  • 14. Session 8 http://www.bized.co.uk Std_logic_vector  Integer Conversions Use conversion functions + type casting i.e. Needs 2 steps. Example Signal A,B : integer; Signal A_std : std_logic_vector (7 downto 0); Signal B_std : std_logic_vector (7 downto 0); A <= to_integer( unsigned( A_std )); B <= to_integer( signed( B_std )); A_std <= std_logic_vector( to_unsigned( A, 8 )); B_std <= std_logic_vector( to_signed( B, 8 )); 14 Copyright 2006 – Biz/ed
  • 15. Session 8 http://www.bized.co.uk Multiplication and Division Operators * / mod rem ** Signal * Constant Z_unsigned <= A_unsigned * 2 ; Size of result = 2 * size of input signal Signal* Signal Signal A_unsigned : unsigned (7 downto 0); Signal B_unsigned : unsigned (7 downto 0); Signal Z_unsigned : unsigned (15 downto 0); Z_unsigned <= A_unsigned * B_unsigned ; Size of result = size of 1st signal + size of 2nd signal Synthesis / mod rem are not synthesis 15 Copyright 2006 – Biz/ed
  • 16. Session 8 http://www.bized.co.uk VHDL is Strongly typed <= Less Errors ; Strong Typing  Strong Error Checking Built into the Compiler less debugging. 16 Without VHDL, you must have a good Testbench+ lots of time to catch your errors. Copyright 2006 – Biz/ed
  • 17. Session 8 http://www.bized.co.uk • Signed Adder Example 35 17 Copyright 2006 – Biz/ed
  • 18. Session 8 http://www.bized.co.uk LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.numeric_std.all ; --------------------------------------- ENTITY adder IS PORT ( Cin : IN STD_LOGIC ; X,Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0); S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); END adder ; --------------------------------------- ARCHITECTURE Behavior OF adder IS SIGNAL Xs,Ys : SIGNED(15 DOWNTO 0); SIGNAL Sum : SIGNED(15 DOWNTO 0); BEGIN Xs <= signed(X); Ys <= signed(Y); Sum <= Xs + Ys + Cin ; S <= std_logic_vector(Sum); END Behavior ; 18 Copyright 2006 – Biz/ed
  • 19. Session 8 http://www.bized.co.uk LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_signed.all ; --------------------------------------- ENTITY adder IS PORT ( Cin : IN STD_LOGIC ; X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)) ; END adder ; --------------------------------------- ARCHITECTURE Behavior OF adder IS BEGIN S <= X + Y + Cin ; END Behavior ; Not Recommended 19 Copyright 2006 – Biz/ed
  • 20. Session 8 http://www.bized.co.uk ENTITY adder16 IS PORT (X,Y: IN INTEGER RANGE -32768 TO 32767 ; S : OUT INTEGER RANGE -32768 TO 32767 ) ; END adder16 ; --------------------------------------- ARCHITECTURE Behavior OF adder16 IS BEGIN S <= X + Y ; END Behavior ; Not Recommended 20 Copyright 2006 – Biz/ed
  • 21. Session 8 http://www.bized.co.uk • UnSigned Adder Example 35 21 Copyright 2006 – Biz/ed
  • 22. Session 8 http://www.bized.co.uk LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.numeric_std.all ; --------------------------------------- ENTITY adder16 IS PORT ( Cin : IN STD_LOGIC ; X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)) ; END adder16 ; --------------------------------------- ARCHITECTURE Behavior OF adder16 IS SIGNAL Xus : UNSIGNED(15 DOWNTO 0); SIGNAL Yus : UNSIGNED(15 DOWNTO 0); SIGNAL Sum : UNSIGNED(15 DOWNTO 0); BEGIN Xus <= unsigned(X); Yus <= unsigned(Y); Sum <= Xus + Yus + Cin ; S <= std_logic_vector(Sum) ; END Behavior ; 22 Copyright 2006 – Biz/ed
  • 23. Session 8 http://www.bized.co.uk LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; --------------------------------------- ENTITY adder16 IS PORT ( Cin : IN STD_LOGIC ; X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)) ; END adder16 ; --------------------------------------- ARCHITECTURE Behavior OF adder16 IS SIGNAL Sum : STD_LOGIC_VECTOR(16 DOWNTO 0) ; BEGIN S <= X + Y + Cin ; END Behavior ; Not Recommended 23 Copyright 2006 – Biz/ed
  • 24. Session 8 http://www.bized.co.uk • Multiplier Example 36 24 Copyright 2006 – Biz/ed
  • 25. Session 8 http://www.bized.co.uk LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all ; --------------------------------------- begin entity multiply is port( -- signed multiplication a : in STD_LOGIC_VECTOR(7 downto 0); sa <= SIGNED(a); b : in STD_LOGIC_VECTOR(7 downto 0); sb <= SIGNED(b); cu : out STD_LOGIC_VECTOR(15 downto 0); sc <= sa * sb; cs : out STD_LOGIC_VECTOR(15 downto 0)); cs <= STD_LOGIC_VECTOR(sc); end multiply; --------------------------------------- -- unsigned multiplication architecture rtl of multiply is ua <= UNSIGNED(a); ub <= UNSIGNED(b); SIGNAL sa: SIGNED(7 downto 0); uc <= ua * ub; SIGNAL sb: SIGNED(7 downto 0); cu <= STD_LOGIC_VECTOR(uc); SIGNAL sc: SIGNED(15 downto 0); end rtl; SIGNAL ua: UNSIGNED(7 downto 0); SIGNAL ub: UNSIGNED(7 downto 0); SIGNAL uc: UNSIGNED(15 downto 0); 25 Copyright 2006 – Biz/ed
  • 26. Session 8 http://www.bized.co.uk • Half Adder Example 37 26 Copyright 2006 – Biz/ed
  • 27. Session 8 http://www.bized.co.uk LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; --------------------------------------- ENTITY HALF_ADDER IS Generic (WIDTH : INTEGER := 8 ); PORT( A : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0 ); B : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0 ); P : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0 ); G : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0 )); END HALF_ADDER; --------------------------------------- ARCHITECTURE RTL OF HALF_ADDER IS BEGIN P <= A XOR B; G <= A AND B; END; 27 Copyright 2006 – Biz/ed
  • 28. Session 8 http://www.bized.co.uk • Full Adder Example 38 28 Copyright 2006 – Biz/ed
  • 29. Session 8 http://www.bized.co.uk LIBRARY ieee; USE ieee.std_logic_1164.all; --------------------------------------- ENTITY fullAdder IS PORT( In1, In2, CarryIn : IN std_logic; Sum : OUT std_logic; CarryOut : OUT std_logic); END fullAdder; --------------------------------------- ARCHITECTURE expr OF fullAdder IS signal temp : std_logic; BEGIN temp <= In1 XOR In2; Sum <= temp XOR CarryIn; CarryOut <= (In1 AND In2) OR (CarryIn AND temp); END expr; 29 Copyright 2006 – Biz/ed
  • 30. Session 8 http://www.bized.co.uk Describe code performing this function C = A + B*2 A,B and C are of width = 16 signed bits C = B*A A,B and C are of width = 16 signed bits lab 15 30 Copyright 2006 – Biz/ed
  • 31. http://www.bized.co.uk Next Part is inside Start Group tutorial [2] Start Group tutorial [2] Prepared by Alaa Salah Shehata Mahmoud A. M. Abd El Latif Mohamed Mohamed Tala’t Mohamed Salah Mahmoud Version 02 – October 2011 Copyright 2006 – Biz/ed
  • 32. Session 8 http://www.bized.co.uk 32 Copyright 2006 – Biz/ed
  • 33. Session 8 http://www.bized.co.uk Design First Data, then Controller Keep it Simple and Stupid (KISS) -VHDL coding is not a -The world’s greatest FSM substitute for design. won’t solve your problems -The best data block is a -Draw a block diagram of in your data blocks. dumb one. your data path using -Make sure your data -Put all of the intelligence familiar building blocks blocks supports your into the controller, where it from digital logic. algorithm. belongs. -Make certain it will work. You can fake FSM signals during simulation while you get your data blocks working. 33 Copyright 2006 – Biz/ed
  • 34. Session 8 http://www.bized.co.uk Code What You Know Generic Your Code Reduce Simulation Time - If you don’t know how a - Generic Codes are easier construct will synthesize, in reading and modifying. - Simulation is a way to don’t use it. debug a design. -If you can’t draw it, you -The more time you spend can’t code it. up front thinking about your design and how it should behave, the less time you will spend simulating. 34 Copyright 2006 – Biz/ed
  • 35. Session 8 http://www.bized.co.uk Avoid Synthesizing Non-Clocked Process Entity Interface Unwanted Latches Latches -USE only In and OUT -FSM output process - All Signals in a non- modes. should define a value for clocked process should be -USE only std_logic and all output signals. in the sensitivity list . std_logic_vectors. -Recommended : Register -Don’t use concurrent - Assign a default value for your output. statements to store all signals. values. 35 Copyright 2006 – Biz/ed
  • 36. Session 8 http://www.bized.co.uk Comments -Don’t think that I can understand all what you say through your code. -Help me with a lot of comments !! And Finally write the Tips you notice when writing your first codes. You will repeat your errors a lot but this way may help you reducing this time. 36 Copyright 2006 – Biz/ed
  • 37. Session 8 http://www.bized.co.uk Questions Session-8 37 Copyright 2006 – Biz/ed
  • 38. Session 8 http://www.bized.co.uk Take Your Notes Print the slides and take your notes here --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- 38 Copyright 2006 – Biz/ed
  • 39. Session 8 http://www.bized.co.uk Take Your Notes Print the slides and take your notes here --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- 39 Copyright 2006 – Biz/ed
  • 40. Session 8 http://www.bized.co.uk See You Next Session 40 Copyright 2006 – Biz/ed