1. ELIMINATION OF DEAD TIME IN PWM
CONTROLLED INVERTERS
Presented by:
Priyambada priyadarshini sahoo
Reg.No:0901106039
Branch: Electrical Engineering

2. OUT LINE
1.what is dead time
.
2.effect of dead time
3.principle of dead time elimination
4.implementation method
5.conclusion

3. WHAT IS DEAD TIME
• To avoid shoot through in pwm controlled vsi a blank time is
introduced
• In this period both upper and lower switches in a phase leg
are off
• So that short circuit can be avoided and switches are not
damaged due to high current

4. single phase half bridge vsi

5. Dead time varies with
1.devices
2.output current
3.temperature
which makes the compensation less effective at low output
Current & low frequency

6. EFFECT OF DEAD TIME
one leg of the inverter single phase full bridge
inverter

7. Considering one leg of the inverter the effect of blanking time
is given in below figure.

8. Comparing the ideal waveform of VAN without blanking time
to actual waveform with blank time the difference between
ideal & actual output voltage is Vϵ=(VAN)ideal-(VAN)actual
By averaging Vϵ over one time period Ts change in output
voltage due to t∆(drop is taken positive)
In leg B of the inverter recognizing that iA= -iB

9. Since Vo=VAN-VBN & io=iA the instantaneous average value
of the voltage difference that is the average value during one
period of the idealized waveform minus the actual waveform
is

10. Plot of instantaneous average effect of blank time on sinusoidal
value Vo as a function of Vref output

11. PRINCIPLE OF DEAD TIME
ELIMINATION
A generic phase leg of VSIs.

12. •Current flowing out of the phase leg is considered as
positive here
• Dead time is not required for p or N switch cells because
both the cells are configured with a controllable switch in
series with a uncontrollable diode
•Gate control signal is selected to gate on or gate off upper
device Kp or lower device Kn only

13. CONTROL SCHEMES
Dead-time elimination control schemes

14. • Determination of load current direction is key for dead time
elimination
• It can be detected by operating status of switches & their anti
parallel diodes instead of expensive current sensors
• Gate signal level is for determination of operating status of
switches
• Diode-conducting detection(DCD) circuit is for determination of
status of anti parallel diode

15. •If D1 is ON the comparator o/p is low, D0 light up otherwise it
is OFF
Diode-conducting detection(DCD) circuit

16. SIMULATION RESULTS
H-bridge voltage source inverter

17. •Load is 8mH inductor & 2.4 ohm resistor
•Vdc is 250v
•Inverter is controlled by unipolar sinusoidal pwm
•Switching frequency 10KHz
•Fundamental frequency of o/p voltage is set to 60Hz

18. Simulated output current waveforms with MI=0.2

19. Comparison of o/p current with 2 usec dead time & without
dead time

20. IMPLEMENTATION METHODS

21. •Two IGBT modules with a load of 8mH &2.4 ohms
resistor
•Four DCD ckts to detect anti-parallel diodes
Dap,Dan,Dbp & Dbn diode
•Output signals of diodes Cap,Can,Cbp,Cbn are fed back
to a complex programmable logic device(CPLD)
•DSP sends two PWM signals Sa & Sb CPLD
•gate signals are achieved by optic electrical interface unit

22. conclusion
•Compared to conventional PWM control with dead time
this method reduces output distortion
•Regains rms value
•Low cost DCD circuits ,simple logic & flexible
implementation
•Avoids using expensive current sensors
•Attractive option for VSI applications

23. REFERNCES
1.http://www.ee.bgu.ac.il/~pedesign/Graduate_problem_pape
rs/papers2007/PWM_Deadtime.pdf
2.Power electronics converters, applications & design Ned
Mohan Tore M. Undeland William P. Robbins
3.Power electronics Dr. P.S. Bimbhra
4.Power electronics Principles & applications Joseph
Vithayathil
5.Power electronics M.H.Rashid

24. THANK YOU