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E.E.E MATLAB PROJECTS, IEEE 2013 PROJECT TITLES
VLSI PROJECT TITLES
VLSI IEEE 2013 PROJECT TITLES
VLSI Projects using Spartan3 FPGA Kit (Spartan3AN FPGA Kit /
Xilinx ISE / Xilinx EDK) & CPLD CoolRunner
SL.NO
TITLES
NVL 001
A Built-In Repair Analyzer With Optimal Repair Rate for Word-Oriented
Memories
NVL 002
A Clock Control Strategy for Peak Power and RMS Current Reduction
Using Path Clustering
NVL 003
A Computationally Efficient Delay less Frequency-Domain Adaptive Filter
Algorithm
NVL 004
A Linear Programming Based Tone Injection Algorithm for PAPR
Reduction of OFDM and Linearly Precoded Systems
NVL 005
A Low-Complexity Turbo Decoder Architecture for Energy-Efficient
Wireless Sensor Networks
NVL 006
A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic
Circuits
NVL 007
Aliasing-Free
Transmitters
NVL 008
Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator
NVL 009
Gate Mapping Automation for Asynchronous NULL Convention Logic
Circuits
NVL 010
Glitch-Free NAND-Based Digitally Controlled Delay-Lines
NVL 011
IsoNet: Hardware-Based
Architectures
NVL 012
Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter with Low
Adaptation-Delay
NVL 013
Broadside and Skewed-Load Tests under Primary Input Constraints
NVL 014
Built-In Generation of Functional Broadside Tests using a Fixed Hardware
Structure
Digital
Pulse-Width
Job
Modulation
Queue
for
Management
Burst-Mode
for
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RF
Many-Core
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E.E.E MATLAB PROJECTS, IEEE 2013 PROJECT TITLES
NVL 015
Design and Implementation of an On-Chip Permutation Network for
Multiprocessor System-On-Chip
NVL 016
Design of Hardware Function Evaluators using Low-Overhead Nonuniform
Segmentation with Address Remapping
NVL 017
Effective and Efficient Approach for Power Reduction by Using Multi-Bit
Flip-Flops
NVL 018
Efficiency Optimization
Transmitters
NVL 019
Efficient Implementation of Reconfigurable Warped Digital Filters With
Variable Low-Pass, High-Pass, Band pass, and Band stop Responses
NVL 020
Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic
Processor Using Heterogeneous Dual-Processing-Element Architecture
NVL 021
Efficient VLSI Implementation of Neural Networks With Hyperbolic Tangent
Activation Function
NVL 022
Eliminating Synchronization Latency Using Sequenced Latching
NVL 023
Error Detection in Majority Logic Decoding of Euclidean Geometry Low
Density Parity Check (EG-LDPC) Codes
NVL 024
Low-Power Area-Efficient High-Speed I/O Circuit Techniques
NVL 025
Low-Power Digital Signal Processor Architecture for Wireless Sensor
Nodes
NVL 026
Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on
Distributed Arithmetic
NVL 027
Low-Resolution DAC-Driven Linearity Testing of Higher Resolution ADCs
Using Polynomial Fitting Measurements
NVL 028
MDC FFT/IFFT Processor With Variable Length for MIMO-OFDM Systems
NVL 029
Multivoltage Aware Resistive Open Fault Model
NVL 030
Oscillation and Transition Tests for Synchronous Sequential Circuits
NVL 031
Power-Planning-Aware
Assignment
NVL 032
RATS: Restoration-Aware
Validation
NVL 033
Reduced-Complexity LCC Reed–Solomon Decoder Based on Unified
Syndrome Computation
for
Soft
Burst-Mode
Error
Trace
Multilevel
Hardening
Signal
via
Selection
Radio
Frequency
Selective
for
Post-Silicon
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Voltage
4. Vision Groups
9603150547
visionsolutions.9@gmail.com
E.E.E MATLAB PROJECTS, IEEE 2013 PROJECT TITLES
NVL 034
Reducing the Cost of Implementing Error Correction Codes in Content
Addressable Memories
NVL 035
Smart Reliable Network-on-Chip
NVL 036
Split-SAR ADCs: Improved Linearity With Power and Speed Optimization
NVL 037
Spur-Reduction Frequency Synthesizer Exploiting Randomly Selected PFD
NVL 038
Static Power Reduction Using Variation-Tolerant and Reconfigurable
Multi-Mode Power Switches
NVL 039
The LUT-SR Family of Uniform Random Number Generators for FPGA
Architectures
NVL 040
Theoretical Modeling of Elliptic Curve Scalar Multiplier on LUT-Based
FPGAs for Area and Speed
NVL 041
Time-Based All-Digital Technique for Analog Built-in Self-Test
NVL 042
Two-Tone Phase Delay Control of Center Frequency and Bandwidth in
Low-Noise-Amplifier RF Front Ends
NVL 043
Unique Measurement and Modeling of Total Phase Noise in RF Receiver
NVL 044
VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture
NVL 045
WLS Design of Sparse FIR Digital Filters
NVL 046
A 10-T SRAM cell with Inbuilt Charge Sharing for Dynamic Power
Reduction
NVL 047
A Current-Starved Inverter-based Differential Amplifier Design for UltraLow Power Applications
NVL 048
A Fast Low-Light Multi-Image Fusion with Online Image Restoration
NVL 049
A High Performance D-Flip Flop Design with Low Power Clocking System
using MTCMOS
NVL 050
A Low Power Fault Tolerant Reversible Decoder using MOS Transistor
NVL 051
A Low Power Single Phase Clock Distribution using VLSI technology
NVL 052
A Novel modulo Adder for 2n-2k-1 Residue Number System
NVL 053
A Novel Transistor Level Realization of Ultra Low Power High-Speed
Adiabatic Vedic Multiplier
NVL 054
A Topology-Based Model for Railway Train Control Systems
NVL 055
Achieving Reduced Area by Multi-Bit Flip Flop Design
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9603150547
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E.E.E MATLAB PROJECTS, IEEE 2013 PROJECT TITLES
NVL 056
An Analysis of SOBEL and GABOR Image Filters for Identifying Fish
NVL 057
An Efficient Denoising Architecture for Removal of Impulse Noise in
Images
NVL 058
An Efficient High Speed Wallace Tree Multiplier
NVL 059
An Efficient SQRT Architecture of Carry Select Adder Design by Common
Boolean Logic
NVL 060
An Interactive RFID-based Bracelet for Airport Luggage Tracking System
NVL 061
Area-Delay Efficient Binary Adders in QCA
NVL 062
Asynchronous Design of Energy Efficient Full Adder
NVL 063
Background Subtraction Based on Threshold detection using Modified KMeans Algorithm
NVL 064
Comparison of Static and Dynamic Printed Organic Shift Registers
NVL 065
CORDIC based Fast Radix-2 DCT Algorithm
NVL 066
Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and
CSLA
NVL 067
Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating
NVL 068
Design of Digit-Serial FIR Filters: Algorithms, Architectures and a CAD
Tool
NVL 069
Design of High Speed Low Power Viterbi Decoder for TCM System
NVL 070
Design of Low Energy, High Performance Synchronous and Asynchronous
64-Point FFT
NVL 071
Design of Low Power Sequential Circuit Using Clocked Pair Shared Flip
flop
NVL 072
FFT Architectures for Real-Valued Signals Based on Radix-2by3 & Radix2by4 Algorithms
NVL 073
Fixed-Width Multipliers and Multipliers- Accumulators with Min-Max
Approximation Error
NVL 074
FPGA Implementation of Pipelined Architecture For SPIHT Algorithm
NVL 075
Hardware Implementation of a Digital Watermarking System for Video
Authentication
NVL 076
High-Throughput Compact Delay-Insensitive Asynchronous NOC Router
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9603150547
visionsolutions.9@gmail.com
E.E.E MATLAB PROJECTS, IEEE 2013 PROJECT TITLES
NVL 077
High-Throughput
Multi
standard
Transform
Core
Supporting
MPEG/H.264/VC-1 using Common Sharing Distributed Arithmetic
NVL 078
Improvement of the Security of Zigbee by a New Chaotic Algorithm
NVL 079
Least Significant Bit Matching Steganalysis based on Feature Analysis
NVL 080
Location-Aware and Safer Cards: Enhancing RFID Security and Privacy via
Location Sensing
NVL 081
Low Latency Systolic Montgomery Multiplier for Finite Field Based on
Pentanomials
NVL 082
Low-Complexity Multiplier for GF (2m) based on All-One Polynomials
NVL 083
Low-Overhead
Fault-Tolerance
Technique
Reconfigurable Soft-core Processor
NVL 084
Low-Power Digital Signal Processing Using Approximate Adders
NVL 085
Memory efficient high-Speed convolution-based generic structure for
multilevel 2D DWT
NVL 086
Modified Gradient Search for Level Set Based Image Segmentation
NVL 087
Multicarrier Systems based on Multistage Layered IFFT Structure
NVL 088
Optical Flow Estimation for Flame Detection in Videos
NVL 089
Parallel AES Encryption Engines for Many-Core Processor Arrays
NVL 090
Performance Analysis of a New CMOS Output Buffer
NVL 091
Performance Evaluation of FFT Processor Using Conventional and Vedic
Algorithm
NVL 092
Pipelined Radix-2k Feed forward FFT Architectures
NVL 093
Prototype of a Fingerprint Based Licensing System For Driving
NVL 094
Real Time Communication between Multiple FPGA Systems in Multitasking
Environment Using RTOS
NVL 095
Reconfigurable Processor for Binary Image Processing
NVL 096
Reduction of Leakage Current and Power in Full Subtractor Using
MTCMOS Technique
NVL 097
Reverse Circle Cipher for Personal and Network Security
NVL 098
RFID-based Location System for Forest Search and Rescue Missions
for
a
Dynamically
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9603150547
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E.E.E MATLAB PROJECTS, IEEE 2013 PROJECT TITLES
NVL 099
RFID-based Tracking
Deforestation
System
Preventing
Trees
Extinction
and
NVL 100
Satellite Image Enhancement Using Discrete Wavelet Transform and
Threshold Decomposition Driven Morphological Filter
NVL 101
Secure Transmission in Downlink Cellular Network with a Cooperative
Jammer
NVL 102
Segmentation and Location of Abnormality in Brain MR Images using
Distributed Estimation
NVL 103
Selective Eigen background for Background Modeling & Subtraction in
Crowded Scenes
NVL 104
Shadow Removal for Background Subtraction Using Illumination Invariant
Measures
NVL 105
Teaching HW/SW Co-Design with a Public Key Cryptography Application
NVL 106
Test Patterns of Multiple SIC Vectors: Theory and Application in BIST
Schemes
NVL 107
The Security Technology and Tendency of New Energy Vehicle in Future
VLSI Projects available only with Simulation
VLSI Projects with Hardware Kit & Simulation - Spartan FPGA 3E KIT
VLSI Projects with Hardware Kit & Simulation - CPLD XL, XC Cool
Runner
VLSI HARDWARE
• SPARTAN 3E KIT
• CPLD XL9572 XC Cool runner
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E.E.E MATLAB PROJECTS, IEEE 2013 PROJECT TITLES
SOFTWARE DETAILS
• Simulation : MODELSIM 6.3G ALTERA
• Implementation : XILINX ISE 12.2
• Language : VHDL / VERILOG
• Power Estimation : Altera XPE or XILINX Power Analyzer
FOR MORE TITLES VISIT OUR OFFICE DIRECTLY
VISIT OUR WEBSITE / BLOGS FOR DOWNLOADS, TITLES & ABSTRACTS
YOUR OWN IDEAS CAN ALSO BE IMPLEMENTED
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E.E.E MATLAB PROJECTS, IEEE 2013 PROJECT TITLES
FINAL YEAR PROJECTS 2013 - 2014
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