2. Chapter 12 - Flip Flop
Lesson Objectives
Upon completion of this topic, you should be able to:
Determine the operations of various types of flip-flops
in digital circuits (e.g. JK flip-flop).
IT2001PA Engineering Essentials (2/2) 2
3. Chapter 12 - Flip Flop
Specific Objectives
Students should be able to :
Draw the symbol of a JK flip-flop.
Explain the characteristics of a JK flip flop with the aid of a truth
table.
Differentiate between edge and level triggered flip flops.
Draw the symbols of :
D type flip flop
JK flip flop and
T flip flop
IT2001PA Engineering Essentials (2/2)
4. Chapter 12 - Flip Flop
Specific Objectives
Students should be able to :
Describe with the aid of truth tables the operation of the following flip flops :
D type flip flop
JK flip flop
T flip flop
Draw the output waveforms of the following flip flops, for a given clock and
control input waveforms:
D type flip flop
JK flip flop
T flip flop
IT2001PA Engineering Essentials (2/2)
5. Chapter 12 - Flip Flop
Specific Objectives
Students should be able to :
Explain the following terms :
Prohibited state
Indeterminate state
Synchronous and
Asynchronous
IT2001PA Engineering Essentials (2/2)
6. Chapter 12 - Flip Flop
Introduction
Flip-flop is digital circuit which functions as a
memory element used in the digital system.
Flip-Flop is made up of an assembly of logic gates.
Even though a logic gate, by itself, has no storage
capability.
Flip-Flop is also known as latch and bi-stable multi-
vibrator.
IT2001PA Engineering Essentials (2/2) 6
7. Chapter 12 - Flip Flop
General Flip-flop Symbol
The symbol shows two
outputs, labeled Q and Q,
that are the inverse of each
other
Q
FF outputs
The FF can has one or
inputs
more inputs. These inputs Q
are used to cause the FF to
switch back and forth
between its possible output
states
IT2001PA Engineering Essentials (2/2) 7
8. Chapter 12 - Flip Flop
General Flip-flop Symbol
Flip-Flop has two allowed
output states.
SET state :- Q
where Q = 1and Q = 0. FF outputs
inputs
Q
RESET state :-
where Q = 0 and Q = 1.
Thus, flip-flop is also known as bi-stable multi-vibrator or latch.
IT2001PA Engineering Essentials (2/2) 8
9. Chapter 12 - Flip Flop
Various Types of Flip-Flops
Unclocked RS flip-flop or latch
Clocked RS flip-flop or gated RS flip-flop
JK flip-flop
D-type latch
D-flip-flop
T-flip-flop
IT2001PA Engineering Essentials (2/2) 9
10. Chapter 12 - Flip Flop
Advantage of JK Flip-Flop
Does not have the problem of a
prohibited input combinations
May be edge-triggered or level-triggered
IT2001PA Engineering Essentials (2/2) 10
11. Chapter 12 - Flip Flop
Positive edge-triggered
Symbol
J Q
CLK
K Q
FF triggers
on positive
transition
IT2001PA Engineering Essentials (2/2) 11
12. Chapter 12 - Flip Flop
Negative edge-triggered
Symbol
J Q
CLK
FF triggers
K Q
on negative
transition
IT2001PA Engineering Essentials (2/2) 12
13. Chapter 12 - Flip Flop
Positive edge-triggered
Logic circuit
J S Q Q
CLK
K R Q Q
IT2001PA Engineering Essentials (2/2) 13
14. Chapter 12 - Flip Flop
Positive edge-triggered
Truth Table
J K CLK Q Remark
0 0 Q O No change
1 0 1 Q = J when J = K
0 1 0 Q = J when J = K
1 1 Q O Toggle state
IT2001PA Engineering Essentials (2/2) 14
15. Chapter 12 - Flip Flop
Positive edge-triggered
Timing diagram
1
J
0
1
K
0
1
CLK
0
a b c d e f g h i j k
1
Q
0
IT2001PA Engineering Essentials (2/2) 15
16. Chapter 12 - Flip Flop
Negative edge-triggered
Operates in the same manner as the positive edge-
triggered except that
output changes states only on the negative
edge of the clock signal.
IT2001PA Engineering Essentials (2/2) 16
17. Chapter 12 - Flip Flop
Negative edge-triggered
Timing diagram
1
J
0
1
K
0
1
CLK
0
a b c d e f g h i j k
1
Q
0
IT2001PA Engineering Essentials (2/2) 17
18. Chapter 12 - Flip Flop
D Flip-Flops
The D flip-flop is also D S Q
called Delay or Data flip-
flop.
R Q
The D flip-flop has only
one input.
It can be easily D J Q
implemented from the RS
or JK inputs as shown.
K Q
IT2001PA Engineering Essentials (2/2) 18
19. Chapter 12 - Flip Flop
D Flip-Flops
Edge-triggered D FF
Truth table
D Clk Q D Q
X 0 no change
CLK Q
0 0
1 1
Q follows D on the“don’t care”of the clock pulse.
“ X ” indicates rising edge
IT2001PA Engineering Essentials (2/2) 19
20. Chapter 12 - Flip Flop
D Flip-Flops
D =1, ClkD Clk == 1, =Q == Q = 0and 0 = 1
D = 0,= = 0, Clk Clk 1 and Q = Q
D and and
Initaily Q = 1
D Q
D
Clk CLK Q
Q
Waveform diagram for a D flip-flop
IT2001PA Engineering Essentials (2/2) 20
21. Chapter 12 - Flip Flop
D Flip-Flops
Level-triggered D FF
Truth table
D EN Q D Q
X 0 no change
EN Q
0 1 0
1 1 1
Q follows D when the FF is enabled; i.e. when EN = 1
IT2001PA Engineering Essentials (2/2) 21
22. Chapter 12 - Flip Flop
D Flip-Flops
D =1,=1, EN0 andand= 0EN EN1 andand=Q = 1
D D =0, EN = D =D == 1 = = 0 Q 1
EN = = 1 1 and Q = 0
Q 1, 0,
Q
“Latched” “Transparent”
Both D and EN inputs are 0, and Q = 0
D Q
D
EN EN Q
Q
Waveform diagram for a D flip-flop
IT2001PA Engineering Essentials (2/2) 22
23. Chapter 12 - Flip Flop
Implementation of the D FF
From the clocked RS FF by
• connecting an INVERTER to the inputs
D S Q D Q
CLK CLK CLK
R Q Q
IT2001PA Engineering Essentials (2/2) 23
24. Chapter 12 - Flip Flop
Implementation of the D FF
From the clocked JK FF by
• connecting an INVERTER to the inputs
D J Q D Q
CLK CLK CLK
K Q Q
IT2001PA Engineering Essentials (2/2) 24
25. Chapter 12 - Flip Flop
Asynchronous Inputs
S R Q Q Remark
0 0 1 1 Prohibited state
0 1 1 0 Set state, Q =1
1 0 0 1 Reset state, Q = 0
1 1 0 1 No change or Hold
IT2001PA Engineering Essentials (2/2) 25
26. Chapter 12 - Flip Flop
Symbol
SET Normal
S Q
INPUTS
ACTIVE FF OUTPUTS
HIGH
R Q
RESET Complementary
SET input set Q-output with a binary ‘1’.
RESET input reset Q-output with a binary ‘0’.
IT2001PA Engineering Essentials (2/2) 26
27. Chapter 12 - Flip Flop
Advantages of synchronous over asynchronous
operation
FF outputs change in orderly manner.
Everything in the system happens at the
same time.
IT2001PA Engineering Essentials (2/2) 27
28. Chapter 12 - Flip Flop
Asynchronous Inputs
Symbol
+5V PRE
Preset & Clear inputs
J Q
• not triggered by clock pulses.
CLK
K Q
CLR
IT2001PA Engineering Essentials (2/2) 28
30. Chapter 12 - Flip Flop
Timing diagram
1
J,K
1
CLK
0
1
PRE
0
1
CLR
0
1
Q
0
a b c d e f g
IT2001PA Engineering Essentials (2/2) 30
31. Chapter 12 - Flip Flop
Operation
Point Operation
a Synchronous toggle on NGT of CLK
b Asynchronous set on PRE = 0
c Synchronous toggle
d Synchronous toggle
e Asynchronous clear on CLR = 0
f CLR over-rides the NGT of CLK
g Synchronous toggle
IT2001PA Engineering Essentials (2/2) 31
32. Chapter 12 - Flip Flop
T Flip-Flops
The T flip-flop is also J Q
called toggle flip-flop.
T
K Q
It can be easily
implemented by High
tying the JK inputs of
the JK FF to high as J Q
shown. CLK
T
K Q
IT2001PA Engineering Essentials (2/2) 32
33. Chapter 12 - Flip Flop
T Flip-Flops
Truth table
Q
Qn Clk Qn+1
T
0 1
Q
1 1
1 0
0 0
IT2001PA Engineering Essentials (2/2) 33
34. Chapter 12 - Flip Flop
T Flip-Flops
Wave format T input
Q
T
Q
Wave form at Q output
fo = 1/2 fin
fo : Output frequency at Q
fin : Input frequency at T
IT2001PA Engineering Essentials (2/2) 34