This 3-day course is designed for digital signal processing engineers, RF system engineers, and managers who wish to enhance their understanding of this rapidly emerging technology. Most topics include carefully described design analysis, alternative approaches, performance analysis, and references to published research results. Many topics are illustrated by Matlab simulation demos. An extensive bibliography is included.

1. 2/6/2014
John Reyland, PhD

2. Software Defined Radio Engineering
Day 1:
• SDR Introduction
• SDR Approaches:
•
•
•
Software Communications Architecture (SCA)
NASA STRS
GNU Radio and Simulink
• SDR Advantage/Disadvantage
• Digital Modulation for SDR
Day 2:
•
•
•
•
RF Channels
Channel Equalization
Multiple Access Techniques
Source and Channel Coding
Day 3:
• Analog Signal Processing
• Digital Signal Processing
2/6/2014
John Reyland, PhD
Stop me
and ask!!!!
2

3. Software Defined Radio Engineering
Basic High Level Structure of a Software Defined Radio:
2/6/2014
John Reyland, PhD
3

4. Software Defined Radio Engineering
The SDR Challenge:
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John Reyland, PhD
4

5. Software Defined Radio Engineering
Economical approach to getting started in SDR
Not shown: GPP feeds back setup commands to reconfigure the radio
2/6/2014
John Reyland, PhD
5

6. Software Defined Radio Engineering
What can you make from these?
• Software defined radio?
• A radio that has a well defined configuration file system that can be setup
for any signal within the limits of available hardware. The key concept is
that hardware and configuration files are flexible enough to be used in the
future for signals and were not anticipated when the radio was first built.
• Switch defined radio?
• A radio that requires the user to choose between a set of explicitly provided
signal functionality. Also called a multimode radio.
• Software designed radio?
• A radio that depends on programed components to process a predefined
signal. A pager or Gen 2 cell phone is an example.
2/6/2014
John Reyland, PhD
6

7. Space Telecommunications Radio System (STRS)
Goal: A single architecture capable of supplying the range of NASA mission classes
NASA requirements range from a small highly optimized radio with severe
size, weight and power constraints to complex radios with multiple operating
frequencies and high data rates. From [S13]:
“The STRS standard provides a common, consistent framework to
develop, qualify, operate and maintain complex reconfigurable and
reprogrammable radio systems. ...
The standard focuses on the key architecture components and
subsystems by describing their functionality and interfaces for both the
hardware and the software including waveform applications. “
2/6/2014
John Reyland, PhD
7

8. Space Telecommunications Radio System (STRS)
2/6/2014
John Reyland, PhD
8

9. Software Communications Architecture (SCA)
A personal computer is based on an architectural infrastructure that establishes
an set of common practices and interfaces for writing applications.
Can a radio be
designed like this?
The US Government
seems convinced!
2/6/2014
John Reyland, PhD

10. Software Communications Architecture (SCA)
A goal of SCA is, from [S2]:
“Provide for the portability of
applications between different
SCA compliant implementations.”
SCA seeks to save time and money by
enabling deployment of SCA
compliant waveform applications on
radio hardware manufactured by
various companies.
2/6/2014
John Reyland, PhD

11. GNU Radio and Simulink
Simulink and GNU Radio comparison:
Simulink runs sample by sample (or frame by frame) simulation steps. Time steps are
locked to the fastest sample rate (however, not all blocks need to change state at this
rate). For each time step, a simulation state is updated. Subtle but important:
simulation states are updated as fast as the CPU can run, but they still match how the
state progression in a hardware sampling clock implementation such as an FPGA.
GNU Radio block diagrams achieve high speed simulation by generating the largest
possible batch of output samples when the scheduler determines the input samples are
available. GNU Radio block processing is event driven, an event (i.e. output data
ready) in an upstream block triggers processing in a downstream block. Items can have
metadata time tags, however this is an add-on that slows down processing..
Both Simulink and GNU Radio are developed in BDEs running on a PC.
However, Simulink seems to have been able to take over a large part of the FPGA
development market.
2/6/2014
John Reyland, PhD
11

12. SDR Advantages
SDR Makes Possible Adaptive Coding and Modulation (ACM):
C WLog2 1
Ps
WN 0
W = Channel bandwidth limit (Hz)
C = Input data rate, not including coding (bits/second)
Ps = Signal power (watts)
N0 = Noise power spectral density (watts/Hz)
R = Actual channel data rate
R<C for arbitrarily low error rate
“Given a discrete memoryless channel [i.e. each signal symbol is
perturbed by Gaussian noise independently of the noise effects on
all other symbols] with capacity C bits per second, and an
information source with rate R bits per second, where R<C, there
exists a code such that the output of the source can be transmitted
over the channel with an arbitrarily small probability of error.”
2/6/2014
John Reyland, PhD
12

13. SDR Advantages
Adaptive Coding and Modulation (ACM):
ACM attempts to take advantage of
the extra BW efficiency available
when link conditions improve
Shannon limit graph is based
on equations from
[A19], page 388
Eb
N0
Eb
N0
2/6/2014
John Reyland, PhD
C
10 Log10
W
2W
C
1
Psignal C
Pnoise W
13

14. SDR Advantages
Adaptive Coding and Modulation:
Given a current and slowly changing set of channel conditions, select a
combination of modulation and channel coding for best throughput. Practical
ACM has two basic requirements:
1.
Current channel conditions must be accurately known and must be slowly
changing. This works best where the receiver can report performance back
to the transmitter over a return channel. Open loop approaches, based on
weather conditions or link distance computed from GPS, may also be
possible. In any case long reporting delays make the system less stable.
Note also that ACM is probably restricted to slow fading channels
2.
The radio must support multiple waveforms at multiple data rates.
2/6/2014
John Reyland, PhD
14

15. SDR Modulation Types
A standard GMSK transmitter design,
let’s discuss each block separately
2/6/2014

16. SDR Modulation Types
Here is the output spectrum showing orthogonal channels spaced 1/12TS apart
f sample
16
MTS
8
MTS
2
MTS
0
2
MTS
8
MTS
f sample
Note that sampling is faster than the original symbol rate: fsample = 4/3Ts
2/6/2014
© John Reyland, PhD
16
16
MTS

17. SDR Modulation Types
We take advantage of the cyclic nature of the IFFT output by adding a block of end
samples to the beginning of each block shifted out.
This prefix has no useful data, however it’s starting phase will be discontinuous with
the phase of the previous block. This discontinuity results in a transient that the receiver
can ignore due to the prefix.
Consider that each block has M user symbol streams on M orthogonal channels.
This means that each symbol in each channel has it’s own prefix, thus multipath echos
occurring during the prefix can be ignored by the receiver
2/6/2014
© John Reyland, PhD
17

18. SDR Modulation Types
Here is how the OFDM circuit is changed to add the cyclic prefix
2/6/2014
© John Reyland, PhD
18

19. RF Propagation Channels
Diversity combining not difficult to implement on uplink:
What about down link from tower to handset? Handset cannot have multiple
receive antennas spaced about ½ wavelength apart, about 16.6 cm at 900 MHz
2/6/2014
© John Reyland, PhD
19

20. RF Propagation Channels
Space-time coding [R12]:
Two base station antennas transmit the same symbols but with different
coding. Receiver has only one antenna. Performance is equivalent to two
receive antenna diversity combining using maximum ratio combining. This is
using in LTE [R10] and wireless LANs [R11].
In this example, transmit signal is: s(t )
s0 , s1
Symbol Time:
Symbols ready to
transmit
Transmit antenna 0
Transmit antenna 1
0
s(0), s(1)
s(0)
s(1)
-s(1)*
s(0)*
s(2)
s(3)
-s(3)*
s(2)*
…
…
1
2
s(2), s(3)
3
…
2/6/2014
….
© John Reyland, PhD
20

21. RF Propagation Channels
Time:
Symbols
ready to
transmit
Transmit
antenna 0
Transmit
antenna 1
0
s(0), s(1)
s(0)
s(1)
-s(1)*
s(0)*
s(2)
s(3)
-s(3)*
s(2)*
…
…
1
2
s(2), s(3)
3
…
r (0)
r (1)
h0 s(0) h1s(1)
h0 s(1)* h1s (0)*

s (0)
*
h0 r (0) h1r * (1)

s (1)
h1*r (0) h0 r * (1)
2/6/2014
….
Signal at receive antenna during the
first two symbol times
Receive decoder has already estimated the channels
and forms these signals
© John Reyland, PhD
21

22. RF Propagation Channels
Doppler frequency shift and
time dilation affect RF channels
where receiver and/or
transmitter are moving relative
to each other
(t )
vr (t ) v(t )cos (t )
Fixed inertial reference frame
2/6/2014
.
v(t )

23. RF Propagation Channels
Some Definitions:
c
Speed of light, 3e8 meters/second
fc
Carrier frequency (Hz)
(t )
Angle between receiver’s forward velocity and
line of sight between transmitter and receiver
vr (t ) v(t )cos
(t )
Velocity of receiver relative to transmitter
f d (t )
Doppler carrier frequency shift at receiver
Tt (t )
Transmit symbol time
Tr (t )
Receive symbol time
2/6/2014

24. RF Propagation Channels
Example 1:
1 GHz = 1e+9 Hz
fc
350 meters/second (constant, approx. Mach 1)
v(t ) v
(t )
vr
0 (constant, worst case for Doppler shift)
v
f d (t )
Velocity of receiver relative to transmitter
fd
Tt (t ) Tt
Tr (t ) Tr
v
c
fc
1e9
1
1e 6
Tt
vTt
c
350
3e8
1e 6
10(350)
1167 Hz
3
Doppler carrier frequency shift at receiver
Transmit symbol time
(1e 6) 1
350
3e8
(1e 6)(1.000001167)
Receive symbol time
This means receive symbol time increases by 0.0001167%. - called time dilation
2/6/2014

25. RF Propagation Channels
d = distance between transmitter and receiver at leading edge of transmit pulse
d+vTt = distance between transmitter and receiver at trailing edge of transmit pulse
d
c
Propagation time at leading edge of transmit pulse
Received Pulse, duration = Tr
d vTt
c
Propagation time at trailing edge of transmit pulse
Transmit Pulse, duration = Tt
d vTt
c
Tt
vTt
c
2/6/2014
d
c
vTt
c
Tt 1
v
c
Additional time duration of pulse at the receiver
Dilated time duration of pulse at the receiver

26. Multiple Access Techniques
Transmitter applies spreading chip sequence:
Receiver applies known transmitter chip sequence to remove spreading:
2/6/2014

27. Multiple Access Techniques
Transmitter applies spreading chip sequence:
Receiver applies INCORRECT transmitter chip sequence, customer data is still spread:
2/6/2014

28. Multiple Access Techniques
De-Spreading results in 10Log(4) = 6dB noise reduction, called Processing Gain:
I
2/6/2014

29. Multiple Access Techniques
Spread Spectrum is used for Multiple Access:
I
2/6/2014

30. Source and Channel Coding
Overview: A real world example - an IS-95 cell phone handset voice channel
Long Code Mask
64000 bps
1200 bps
2400 bps
4800 bps
9600 bps
Convolutional
Encoder
Rate 1/3, k=9
3600 bps
7200 bps
14400 bps
28800 bps
Symbol
Repetition
8
4
2
0
Block
Interleaver
28800 bps
28800 bps
Walsh
Code
Modulator
I-Chan Chips
1.2288 Mcps
Data Burst
Randomizer
307200 cps
Q-Chan Chips
1.2288 Mcps
We will discuss each block in detail …
2/6/2014
To Offset QPSK Modulator
Variable
Rate
Vocoder
Interleaving
Isolates
Errors
1.2288 Mcps
Speech
Samples
Channel
Coding
Adds
Redundancy
1.2288 Mcps
Source
Coding
Removes
Redundancy
Long Code
Generator
Spectrum
Spreading
for
processing
gain

31. Source and Channel Coding
Step 7: Traceback from largest final PM
Note traceback bit sequence: 1 1 1 0 1, reversed = 1 0 1 1 1 = transmit bit sequence
2/6/2014
© John Reyland, PhD
31

32. Channel Equalization Techniques
Raised cosine pulses have an extremely important attribute: at the ideal
sampling points, they don’t interfere with each other
Over an ideal channel, delayed transmit signal will be observed at the receiver.
Ideal channel:
sreceived (t )
stransmit (t
)
John Reyland, PhD
2/6/2014

33. Channel Equalization Techniques
Intersymbol Interference (ISI) comes about due to imperfect channels:
yreceive (n) 0.5x n 1
x n
0.5x n 1
Green = postcursor, occurs prior to the main sample
Blue = main sample in this illustration
Yellow = precursor, occurs after the main sample
John Reyland, PhD
2/6/2014

34. Channel Equalization Techniques
For this simple channel, we can calculate the effect of ISI:
x(n-1)
x(n)
x(n+1)
Received signal, no ISI
Received signal, ISI
-1
-1
-1
-1
-2 = -0.5-1-0.5
-1
-1
1
-1
-1 = -0.5-1+0.5
-1
1
-1
1
0 = -0.5+1-0.5
-1
1
1
1
1 = -0.5+1+0.5
1
-1
-1
-1
-1 = 0.5-1-0.5
1
-1
1
-1
0 = 0.5-1+0.5
1
1
-1
1
1 = 0.5+1-0.5
1
1
1
1
2 = +0.5+1+0.5
Primary effect of ISI is to degrade the BER . Simple BER calculations are no longer valid:
P(bit error) Q
2 Eb
N0
For the non-ISI case becomes much
more complicated with ISI
John Reyland, PhD
2/6/2014

35. Analog Signal Processing
Continuing on, we can calculate the receiver noise at the ADC input
Composite Noise Figure up to the VGA output:
NFRxdB
10 Log10 F0
Composite Gain (max AGC gain):
PRXnoisedBm
2/6/2014
F1 1 F2 1 F3 1
G0
G0G1 G0G1G2
F4 1
G0G1G2G3
GRXdB 10Log10 G0G1G2G3G4
PNdBm
NFRXdB GRXdB
© John Reyland, PhD
35

36. Analog Signal Processing
Composite ADC noise floor consists of receiver noise plus ADC noise:
Start by converting receiver noise at the ADC input to a voltage:
VRXnoise
G5 RADC 10
PRXnoisedBm
3
10
G5 = 2 = transformer
turns ratio. RADC =
ADC input resistance
Given the ADC data sheet SNR rating, calculate the ADC generated input noise voltage:
VADCnoise
VFS , RMS 10
SNR /20
We assume these two are normally distributed random variables, therefore we sum the
variance and take the square root to get back to a composite ADC noise floor voltage
VNoiseFloorADC
2/6/2014
2
2
VADCnoise VRXnoise
© John Reyland, PhD
Typically < 0.5 milliVolt.
Note that both voltages
are measured across RADC
36

37. Analog Signal Processing
ADC dynamic range details for one in-band signal:
Signal power must be
backed off by peak to
average power ratio (PAPR).
For OFDM:
20 log10
VFS
VADC max
8dB
Minimum SNR required
by the modulation type:
SNRMin
Note: ADC driver amplifier must also
have sufficient dynamic range
2/6/2014
© John Reyland, PhD
20log10
VADC min
VNoiseFloorADC
37

38. Digital Signal Processing
Packet payloads generally use more complicated bandwidth efficient modulation
A simple example where the packet data length is based on the interleaver size:
2/6/2014
John Reyland, PhD

39. Digital Signal Processing
We will organize the SDR DSP discussion around the receiver architecture below:
This setup is suitable for many linear modulations in common use today:
• Nonlinear demodulation would replace equalizer with phase discriminator and
also probably not have carrier tracking
• CDMA would required additional code synchronization circuits
• OFDM would require an FFT to separate subcarriers
2/6/2014
John Reyland, PhD

40. Digital Signal Processing
Intermediate center frequency Fif = 44.2368 MHz.
Does this mean sampling frequency Fs > 88.4736 MHz ?
No, we can bandpass sample, by making Fs = (4/3) Fif = 58.9824 MHz. This has advantages:
• Lower sample rate => smaller sample buffers and fewer FPGA timing problems
• Fif can be higher for the same sample rate, this may make frequency planning easier
Disadvantage is that noise in the range [Fs/2 Fs] is folded back into [0 Fs/2]
2/6/2014
John Reyland, PhD

41. Digital Signal Processing
Complex basebanding process in the frequency domain, ends with subsampled Fs = 29.491 MHz
2/6/2014
John Reyland, PhD

42. Digital Signal Processing
Halfband Filter response
HalfBand filter Impulse Response, Order=11
0.6
0.4
Typical Matlab code:
0.2
0
-0.2
Fss = 58.9824e6;
1
2
3
4
5
6
7
8
9
10
11
Resp, dB
0
-10
-20
-30
-40
0
3.6864
7.3728
11.0592 14.7456 18.432
Frequency (MHz)
22.1184 25.8048 29.4912
% Check frequency response
[hb,wb] = freqz(b,1,2048);
plot(wb,10*log10(abs(hb)));
set(gca,'XLim',[0 pi]);
set(gca,'XTick',0:pi/8:pi);
set(gca,'XTickLabel',(0:(Fss/16):(Fss/2))/1e6);
Resp, linear
1
0.5
0
% Setup halfband filter for input subsampling
PassBandEdge = 1/2-1/8;
StopBandRipple = 0.1;
b=firhalfband('minorder', …
PassBandEdge, …
StopBandRipple, …
'kaiser');
0
3.6864
2/6/2014
7.3728
11.0592 14.7456 18.432
Frequency (MHz)
22.1184 25.8048 29.4912
John Reyland, PhD

43. Digital Signal Processing
DSP Circuits for IF to Complex BB process
Fs/4 Local Oscillator
Inphase Halfband Filter
I(n) + jQ(n) = [1+j0,0+j1,-1+j0,0-j1,1+j0, ...]
HI(z) = h0 + z-2h2 + z-3h3 + z-4h4 + z-6h6
Ib(n)
x(n)
Z-1
h0
Z-1
Z-1
Z-1
Z-1
Z-1
0
h2
h3
h4
0
h6
Ihb(n)
2
Qb(n)
Z-1
h0
Z-1
Z-1
Z-1
Z-1
Z-1
0
h2
h3
h4
0
h6
Qhb(n)
2
Quadrature Halfband Filter
HQ(z) = h0 + z-2h2 + z-3h3 + z-4h4 + z-6h6
2/6/2014
John Reyland, PhD

44. Digital Signal Processing
Input
Samp.
Index @
Fs
Local
Oscillator:
I(n) + jQ(n) =
Mixer Output
Quadrature Halfband Filter Tap Signals
x(n)
x(0)
x(1)
x(2)
x(3)
x(4)
x(5)
x(6)
x(7)
I(n)
1
0
-1
0
1
0
-1
0
Q(n)
0
1
0
-1
0
1
0
-1
Ib(n)
x(0)
0
-x(2)
0
x(4)
0
-x(6)
0
Qb(n)
0
x(1)
0
-x(3)
0
x(5)
0
-x(7)
h0
0
x(1)
0
-x(3)
0
x(5)
0
-x(7)
0
0
0
x(1)
0
-x(3)
0
x(5)
0
h2
0
0
0
x(1)
0
-x(3)
0
x(5)
h3
0
0
0
0
x(1)
0
-x(3)
0
h4
0
0
0
0
0
x(1)
0
-x(3)
0
0
0
0
0
0
0
x(1)
0
h6
0
0
0
0
0
0
0
x(1)
x(8)
x(9)
1
0
0
1
x(8)
0
0
x(9)
0
x(9)
-x(7)
0
0
-x(7)
x(5)
0
0
x(5)
-x(3)
0
0
-x(3)
x(10)
x(11)
-1
0
0
-1
-x(10)
0
0
-x(11)
0
-x(11)
x(9)
0
0
x(9)
-x(7)
0
0
-x(7)
x(5)
0
0
x(5)
x(12)
x(13)
1
0
0
1
x(12)
0
0
x(13)
0
x(13)
-x(11)
0
0
-x(11)
x(9)
0
0
x(9)
-x(7)
0
0
-x(7)
x(14)
x(15)
-1
0
0
-1
-x(14)
0
0
-x(15)
0
-x(15)
x(13)
0
0
x(13)
-x(11)
0
0
-x(11)
x(9)
0
0
x(9)
2/6/2014
John Reyland, PhD
Quadrature Half Band Output
@ sample rate = Fs/2
0
x(1)*h0
0
-x(3)*h0 + x(1)*h2
x(1)*h3
x(5)*h0 - x(3)*h2 + x(1)*h4
-x(3)*h3
-x(7)*h0 + x(5)*h2 - x(3)*h4 +
x(1)*h6
x(5)*h3
x(9)*h0 - x(7)*h2 + x(5)*h4 x(3)*h6
-x(7)*h3
-x(11)*h0 + x(9)*h2 - x(7)*h4 +
x(5)*h6
x(9)*h3
x(13)*h0 - x(11)*h2 + x(9)*h4 x(7)*h6
-x(11)*h3
-x(15)*h0 + x(13)*h2 - x(11)*h4
+ x(9)*h6

45. Digital Signal Processing
Final Design: Fs/4 downconvert, halfband filter and subsample by 2
2/6/2014
John Reyland, PhD

46. Digital Signal Processing
After subsampling to Fs = 29.491 MHz, we can filter with an arbitrary low
pass filter to reject as much noise as possible:
We can also subsample further to reduce processing load
2/6/2014
John Reyland, PhD

47. Digital Signal Processing
A popular filter and decimate circuit is the cascaded integrator comb (CIC) filter
u( z )
x( z )
1 z
1 z
1 z
1 z
2/6/2014
1
1
1 z
4
1
1 z
1 z
1 z
1
2
1
1
jz
1 z1
jz 1 1 jz
2
1
1
1
jz
1
1
John Reyland, PhD

48. Digital Signal Processing
This CIC filter has the same frequency response as a 4 tap boxcar filter, see [D2]
2/6/2014
John Reyland, PhD

49. Digital Signal Processing
Downsample by 4 shown as 2
downsamples by 2.
Two CIC problems:
• Spectral droop applied to desired
signal (blue)
• Aliasing into desired signal
bandwidth
2/6/2014
John Reyland, PhD