This document discusses high performance computing and topics related to cache coherence and vector processing. It provides an overview of cache coherence approaches including write-back and write-through implementations. It also describes hardware-based cache coherence solutions like directory and snoopy protocols. The directory protocol uses a centralized controller while snoopy protocol relies on broadcast messages. Specific cache coherence protocols like MESI and write-invalidate are explained. Vector processing and Amdahl's law on parallel programming speedup are also briefly mentioned.

1. High Performance Computing JawwadShamsi Lecture #6 27th January 2010

2. Recap Cache Coherence NUMA

3. Today’s topics Cache Coherence – Continuation Vector Processing

4. Cache Coherence In SMP or NUMA, multiple copies of cache Each copy may have a different value of data item Maintain Coherency How?

5. Cache Coherence: Two Approaches Write back: Update Main memory once cache is flushed. Write through: Write is updated to cache as well as to the main memory.

6. Implementations Software Solutions: Compile time decision Conservative Inefficient cache utilization Hardware Solutions: Runtime decision More effective

7. Hardware based solution Directory Protocol Snoopy Protocol

8. Directory Centralized Controller Individual cache controller makes a request Centralized controller checks and issues command Updates information

9. Directory Write Processor requests exclusive writes Controller sends message Invalidates Read Issues command to the processor Holding Processor Writes back to MM Read permitted

10. Directory Disadvantage Centralized Controller Bottleneck Advantage Useful in large –scale system

11. Snoopy Protocol Update operation announced All Cache controllers snoop Bus architecture Careful Increased Bus Traffic

12. Snoopy Protocol Two approaches Write Invalidate One write Multiple readers Exclusive: Writer invalidates others entries Write Update Multiple writers All writes are updated

13. Write Invalidate The MESI Protocol : P4 processor Data cache: Two status bits, 4 states Modified Exclusive Shared Invalid See Table

14. 4 Possibilities Read Miss: EX to SH SH to SH MO to SH Read-Hit Write-Miss RWITM MO to IN SH to IN Write Hit SH to IN EX Mo

15. L1- L2 Cache Consistency

16. Parallel programming and Amdahl's Law Suppose 1/N time for sequential code And 1-1/N for the parallel

17. Amdahl's Law Speedup: speed gain of using parallel processor vs. single processor Speed= 1/(s+(p/N)) S=sequential code, p = parallel code, N= no. of processors S= T(1)/ T(j) For j parallel processors As problem size increases, p may rise and s may decrease