LMAX Architecture
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LMAX is a concurrent architecture optimized for high throughput. It is optimized for SEDA architectures.
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LMAX Architecture
- 1. Die LMAX-Architecture with Disruptors: 6M Transactions per Second Stephan Schmidt, Vice CTO, brands4friends
- 2. Me Stephan Schmidt Vice CTO brands4friends @codemonkeyism www.codemonkeyism.com stephan.schmidt@brands4friends.de
- 3. 3
- 5. brands4friends No.1 Shopping Club in Germany > 360k daily visitors > 4.5M Users eBay company 5 20.04.12 WJAX 2011
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- 7. 7
- 8. Development at brands4friends Team Java and web developers, data warehouse developers Process Scrum since 2009 Kanban for DWH since 2012
- 9. LMAX - The London Multi-Asset Exchange "We aim to build the highest performance financial exchange in the world" 9 20.04.12 Fußzeilentext
- 10. High Performance Transaction Processing 10 20.04.12 Fußzeilentext
- 11. Business Receive Unmarshal Journal Replicate Marshall Send Logic Service / Transaction Processor
- 12. Business Receive Unmarshal Journal Replicate Marshall Send Logic Queue Queue Queue Queue Queue Queue Service / Transaction Processor
- 13. Cores Ghz CPU
- 14. Actors? SEDA? 14 20.04.12 Fußzeilentext
- 15. Stuff that did not work for various reasons 1. RDBMS 2. Actors Receive Unmarshal Journal Replicate Business Logic Marshall Send Queue Queue Queue Queue Queue Queue 3. SEDA Service / Transaction Processor 4. J2EE … 15 20.04.12 Fußzeilentext
- 16. LMAX Architecture 16 20.04.12 Fußzeilentext
- 17. Business Receive Unmarshal Journal Replicate Marshall Send Logic Queue Queue Queue Queue Queue Queue Service / Transaction Processor
- 18. Size Linked List Queue Node Node Node Node Add Remove Add Remove Array Queue Cache Line Cache Line
- 19. Queue as a data structure Problems with Queues 1. Reading (Take) and Writing (Add) are both write access => Write Contention 2. Write Contention solves with Locks 1. Other solutions include Deques 3. Locks lead to context switches to the kernel 1. Context switches lead to CPU cache misses etc. 2. Kernel might use opportunity to do other stuff as well 19
- 20. Locks Costs according to LMAX Paper Method Time in ms Single Thread 300 Single Thread mit Lock 10.000 Zwei Threads mit Lock 224.000 Single Thread mit CAS 5.700 Zwei Threads mit CAS 30.000 Single Thread/ 4.700 Volatile Write “Compare And Swap” Atomic Reference etc. in Java => No Context Switch Memory Read/Write Barrier 20
- 21. LMAX Data Structure – Ring Buffer Event Publisher Processor Ring Buffer 21
- 22. Pre-Allocation of Buckets 31 30 29 28 0 27 1 26 2 25 3 24 4 23 5 22 Event Publisher 6 21 Processor 7 20 8 19 9 18 10 17 11 16 12 15 13 14 Ring Buffer 2^5 • No (less) GC problems • Objects are near each other in memory 22 => cache friendly
- 23. Coordination 31 30 29 28 0 27 1 26 2 25 3 24 4 23 5 22 Event Publisher 6 21 Processor 7 20 Claim 8 19 Wait Strategy 9 18 Strategy 10 17 11 16 12 15 13 14 Ring Buffer 2^5 1.Claim 2.Write 3.Make Public by advancing sequence 23
- 24. Latency Business Receive Unmarshal Journal Replicate Marshall Send Logic Queue Queue Queue Queue Queue Queue Service / Transaction Processor
- 25. Journal Receive Replicate Business Message Logic Unmarshall
- 26. Business Receive Unmarshal Journal Replicate Marshall Send Logic Datenstruktur Datenstruktur Service / Transaction Processor
- 27. LMAX Architektur Input Disruptor Ouput Disruptor Ouput Disruptor Ouput Disruptor Business Logic Handler
- 28. HA Node Publisher Receiver Replicator Marshaller Journaler Un- Marshaller Output Disruptor Input Disruptor File System Jede Stage kann mehrere Business Logic Handler Threads haben 28
- 29. Receiver writes on 31. Journaler and Replicator read on 24 and can move up the Receiver sequence to 30. Journaler 31 Replicator 24 Un-Marshaller can move beyond Un- Journaler and Replicator up to Marshaller 30. 19 18 Business Logic Handler needs Business Logic to stay behind all others. Handler 29
- 30. Java API 30 20.04.12 Fußzeilentext
- 33. C1 P1 C2 C3 C4
- 34. C2 P1 C1 C3 C4
- 35. C1 C2 P1 C3 C4
- 36. C2 P1 C1 C4 C3
- 37. P1 C1 P2
- 38. Demo 38 20.04.12 Fußzeilentext
- 39. LMAX Low Level Ideas 1. Simple Code 2. Everything in memory 3. Single threaded per CPU for business logic 4. Business logic has no I/O, I/O is done somewhere else 5. Scheduler “knows” dependencies of handlers 39 20.04.12 Fußzeilentext
- 40. 6M TPS? How did LMAX do it? x 10 x 10 3 billions of 1000K+ TPS instructions on modern Custom, cache friendly CPU collections 100K+ TPS Performance Testing Clean organized code Controlled GC Standard libraries 10K+ TPS Very well modeled domain If you don't do anything stupid 40
- 41. We’re looking for very good developers
- 43. Images CC from Flickr: nimboo, imjustcreative, gremionis, justonlysteve, John_Scone, Matthias Wicke, irisgodd3ss, TunnelBug, alandd, seasonal wanderer, raulbarraltamayo, Gilmoth, Dunechaser, graftedno1 43
- 44. Sources “Disruptor: High performance alternative to bounded queues for exchanging data between concurrent threads”, Martin Thompson, Dave Farley, Michael Barker, Patricia Gee, Andrew Stewart, 2011 "The LMAX Architecture”, Martin Fowler, 2011 http://martinfowler.com/articles/lmax.html “How to do 100K+ TPS at less than 1ms latency”, Martin Thompson, Michael Barker, 2010 44 20.04.12 Fußzeilentext