In recent years Sigma-Delta ADCs became one of the most popular types of Analog-to-Digital converters. The key features of these are high-speed, high resolution and low operating voltages. These are commonly used in variety of applications like digital audio CDs, CODEC, biomedical sensor applications and wireless transmitters/receivers. The basic principles involved in this technique are oversampling and noise shaping. This report reviews different techniques proposed for high resolution, low power Sigma-Delta ADC. Conventional design of SDM was dominated by discrete time architecture but in modern designs continuous types are also becoming famous because of their low power attributes. Continuous efforts have been taken to reduce the supply voltages of SDM and recently, lowest reported is 250mv.

1. Sigma-Delta Analog to Digital Converters
(ADCs)
Satish Patil
Dept. of Electrical Engineering
Indian Institute of Techology, Bombay
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2. Outline
Basic principle
Eect of oversampling and noise shaping
1st and 2nd -order modulator (MOD1 and MOD2)
Eect of Noise shaping on total noise
Issues in modulator design
Discrete and Continuous time realization
Inherent anti-aliasing property of CT modulators
Eect of Quantizer bits
Maximum stable amplitude
Loop

3. lter architectures
Multi-stage (Cascaded) modulators
Design example
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4. Block diagram of ADC
General bolck diagram
2 major parts- Modulator and Decimator
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5. Basic principle of Sigma-Delta () modulator
Oversampling + Noise shaping
Oversampling: sampling input signal with frequency multiples of
Nyquist rate - Over Sampling Ratio (OSR)
Noise shaping: selecting proper loop transfer function such that
spectral density of inband noise can be reduced
Key features: coarse quantization,

6. ltering,feedback
Quantization is often quite coarse (1 bit!), but the eective resolution
can still be as high as 10-22 bits.
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7. Eect of oversampling and noise shaping
0
Reference: Industrial Sigma Delta Convertors Overview, Analog Devices Webcast Technical Seminar Series
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8. 1st-order modulator (MOD1)
Vo(z) = Ui (z):z1 + En(z):(1 z1)
STF = z1; NTF = (1 z1)
out of band gain (gain at z = 1) or jjHjj1 = 2
jNTF(ej!)j j!
= j1 ej!j = je
2 ej!
2 j = 2sin(!2
) at low
frequencies(approx.) jNTF(ej!)j !
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9. 2nd-order modulator (MOD2)
Vo(z) = Ui (z):z2 + En(z):(1 z1)2
STF = z2; NTF = (1 z1)2
jjHjj1 = 4
jNTF(ej!)j = j1 ej!j2 = je
j!
2 ej!
2 j2 = 4sin2(!2
) at low
frequencies(approx.) jNTF(ej!)j !2
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10. Noise performance
Inband Quantization noise power = 2
12
R
OSR
0 jNTF(j!)j2d!
For 1st order SDM,
Inband Quantization noise power = 2
12
R
OSR
0 !2d! = 2
12
13
3
OSR3
For every doubling in OSR, noise power decreases by factor of 8 hence
increase in eective no. of bits (ENOB) 1.5bits
For 2nd order SDM,
Inband Quantization noise power = 2
12
R
OSR
0 !4d! = 2
12
15
5
OSR5
Increase in ENOB for every doubling in OSR 2.5bits1
1
Reference: online video lectures of VLSI Data conversion circuits(EE658), IIT Madras
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11. Noise shaping
Figure: Noise shaping vs order Figure: zoomed portion
Out of Band gain increases with very rapidly with increase in
modulator order
Better inband, Worst out of band noise performance!
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12. Eect of Noise shaping on total noise
Total Q. noise power is calculated by 2
12
R
0 jNTF(j!)j2d!
MOD1: with only oversampling, STF = 1, NTF = 1, total noise
power is 2
12
with oversampling noise shaping, STF = 1,
NTF = (1 z1), total noise power is 2
12 2 = 22
12
MOD2: with only oversampling, STF = 1, NTF = 1, total noise
power is 2
12
with oversampling noise shaping, STF = 1,
NTF = (1 z1)2, total noise power is 62
12
Noise shaping results in increase in total Q.noise!
this phenomenon even gets worse for higher order modulators
Total P
noise can also be derived using Parseval's theorem:
2
12
k
h2(k) = 2
12
R
0 jNTF(j!)j2d!
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13. Issues in modulator design
SNR for oversampled noise shaping converter is
SNRdB = 6:02B + 1:76 + 10log ( 2L+1
2L ) + (2L + 1)log10(OSR) where,
B=quantizer bits
L=order of modulator
OSR=oversampling ratio
Ways to improve SNR
i. increasing loop order
ii. increasing OSR
iii. increasing quantizer resolution
Higher order modulators are highly unstable. This issue can be
addressed by using multi stage noise shaping (MASH) architecture.
quantizer overloading issue can be checked by MSA simulation
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14. Block diagram of CT and DT ADC
Contineous-time SDM provides inherent anti-aliasing
performance of CT is highly volatile to shape of pulse used for DAC2
2
source: Jose M de la Rosa. Sigma-delta modulators: Tutorial overview, design guide, and state-of-the-art
survey. Circuits and Systems I: Regular Papers, IEEE Transactions on, 58(1):121, 2011
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15. SNR vs OSR
Figure: SNR vs oversampling ratio for dierent modulator orders3
3
All MATLAB simulations are carried using R.Schreier, Toolbox, online available :
http://www.mathworks.com/matlabcentral/

16. leexchange19
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17. Inherent anti-aliasing property of CT modulators
Figure: 1st order modulator with Anti-aliasing

18. lter
Figure: 1st order continuous time modulator
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19. Inherent anti-aliasing property of CT modulators...
Figure: CT MOD1 after block adjustment
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20. Inherent Anti-Aliasing property of CT modulators...
Figure: Frequency response of MOD1 CT modulators
unlike DT modulator, response to and 1 + is not same.
For higher orders, alias rejection response of CT modulators gets
better and better!
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21. Eect of Quantizer bits
nLev SNR(in dB) MSA=VRef
2 135 0.703
4 141.8 0.834
8 149.3 0.874
16 157.4 0.889
32 163.4 0.894
64 166.4 0.898
Results shown above are for order=3, OSR=256, N=8192
Risbo's method is used for calculation of MSA.
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22. Eect of Quantizer bits (order=2, OSR=64)
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23. Maximum Stable Amplitude(MSA)
Idea: apply slowly increasing ramp input over suciently large points
(1 Mega points) and

24. nd when y crosses threshold point.
Figure: input ramp and observed output of modulator
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25. MSA cont'd
Figure: time domain output of waveform used to calculate MSA
MSA: 90% of input where y blows away (in this case, y blows away
for input=0.97 of fullscale)
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26. Loop

27. lter architectures
Feedback topologies
I Cascade of Integrators Feedback form (CIFB)
I Cascade of Resonators Feed-forward form (CRFB)
lower power consumption at expense of higher distortion and
complexity of multiple feedback DACs
Feed-forward topologies
I Cascade of Integrators Feedback form (CIFF)
I Cascade of Resonators Feed-forward form (CRFF)
Low signal distortion.
only one DAC is required in feedback loop but extra ampli

28. er is needed
to accurately sum up input and integrator output4
4
J. Silva, U. Moon, J. Steensgaard, and G. Temes. Wideband lowdistortion delta-sigma ADC topology,
Electron. Lett., vol. 37, no. 12, pp. 737-738, Jun. 2001.
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29. Loop

30. lter architectures...
Figure: CIFB Figure: CRFB
Figure: CIFF Figure: CRFF
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31. Multi-stage (Cascaded) modulators
Higher-order noise shaping can be achieved by cascading

32. rst-order
modulators
The

33. rst modulator converts the
analog input signal
Each subsequent modulator
converts the quantization error
from the previous modulator
The quantization noises are
digitally cancelled
This gives a higher order of
noise shaping, without causing
instability
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34. Multi-stage (Cascaded) modulators...
y1(z) = x1(z)z1 + e1(z)(1 z1) and
y2(z) = e1(z)z1 + e2(z)(1 z1)
so output y(z) = y1(z)z1 + y2(z)(1 z1)
) y(z) = x(z)z2 + e2(z)(1 z1)2
Advantage: 2nd order noise shaping is achieved though 1st order loop
is implemented
However, cancellation of e1 is not perfect since the analog transfer
functions are not ideal
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35. Design Example
Design speci

36. cations:
I input frequency=500Hz
I SNR 100dB (16 bit resolution)
I use 1-bit quantizer
we design modulator for 17 bit resolution. 1st and 2ndorder loop

37. lters improves SNR by 9dB (1.5bits) and 15dB (2.5bits) per octave.
increment needed in resolution=16 bits, hence
I If L=1, then OSR 2
16
1:5 ) OSR = 2048
I If L=2, then OSR 2
16
2:5 ) OSR = 256
since case of 2048 OSR is dicult to implement we go for OSR=256,
order=2. NTF obtained using these specs:
TF = z22z+1
z21:225z+0:441
for 2nd order modulator H(1) = 2, we select jjHjj1 = 1:5 which
ensures stability and avoid quantizer overload
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38. Design Example...
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39. Design Example...
SNR achieved from simulations: 100.9dB
MSA obtained by Risbo's method: 90% of Vref
for CRFB topology coecients obtained are as:
a : 0.2163 0.5585
g : 5.0199e-05
b : 0.2163 0.5585 1.0000
c : 1 1
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40. References I
Jose M de la Rosa.
Sigma-delta modulators: Tutorial overview, design guide, and state-of-the-art survey.
Circuits and Systems I: Regular Papers, IEEE Transactions on, 58(1):1{21, 2011.
Shanthi Pavan and Prabu Sankar.
Power reduction in continuous-time delta-sigma modulators using the assisted opamp technique.
Solid-State Circuits, IEEE Journal of, 45(7):1365{1379, 2010.
Youngcheol Chae and Gunhee Han.
Low voltage, low power, inverter-based switched-capacitor delta-sigma modulator.
Solid-State Circuits, IEEE Journal of, 44(2):458{472, 2009.
Chia-Ling Chang and Jieh-Tsorng Wu.
A 1-v 100-db dynamic range 24.4-khz bandwidth delta-sigma modulator.
In Circuits and Systems (ISCAS), 2013 IEEE International Symposium on, pages 813{816. IEEE, 2013.
Dushyant Juneja, Sougata Kar, Procheta Chatterjee, and Siddhartha Sen.
Design of delta sigma modulators for integrated sensor applications.
Control Theory and Informatics, 3(2):25{34, 2013.
J Silva, U Moon, J Steensgaard, and GC Temes.
Wideband low-distortion delta-sigma adc topology.
Electronics Letters, 37(12):737{738, 2001.
Fridolin Michel and Michiel SJ Steyaert.
A 250 mv 7.5 w 61 db sndr sc modulator using near-threshold-voltage-biased inverter ampli

41. ers in 130 nm cmos.
Solid-State Circuits, IEEE Journal of, 47(3):709{721, 2012.
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42. References II
Younghyun Yoon, Hyungdong Roh, Hyuntae Lee, and Jeongjin Roh.
A 0.6-v 540-nw delta-sigma modulator for biomedical sensors.
Analog Integrated Circuits and Signal Processing, pages 1{5, 2013.
Hao Luo, Yan Han, Ray CC Cheung, Xiaopeng Liu, and Tianlin Cao.
A 0.8-v 230-w 98-db dr inverter-based modulator for audio applications.
2013.
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