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“ SHARED MEMORY” MADE BY: SANJANA BAKSHI 7IT087 A PPT ON
TOPICS TO BE COVERED: ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
What is a DSM system? ,[object Object],[object Object],[object Object],[object Object]
What is shared memory? ,[object Object],[object Object],[object Object],[object Object]
Various architectures to be discussed: ,[object Object],[object Object],[object Object]
On Chip Memory ,[object Object],[object Object],[object Object]
[object Object],CPU Memory CPU1 Memory CPU4 CPU2 CPU3 Chip package Address and data lines Connecting the CPU to the  memory extension A single-chip computer A hypothetical shared-memory Multiprocessor.
What is a bus??? ,[object Object],[object Object]
Bus-based multiprocessors Bus-based multiprocessors BUS BASED MULTIPROCESSORS SMP :   Symmetric Multi-Processing All CPUs connected to one bus (backplane) Memory and peripherals are accessed via shared bus. System looks the same from any processor. Bus CPU A CPU B memory Device I/O
Bus-based multiprocessors Dealing with bus overload  - add local memory CPU does I/O to cache memory - access main memory on cache miss Bus memory Device I/O CPU A cache CPU B cache
Working with a cache CPU A reads location 12345 from memory Bus 12345:7 Device I/O CPU A 12345: 7 CPU B
Working with a cache CPU B reads location 12345 from memory Gets old value Memory not coherent! Bus 12345:7 Device I/O CPU A 12345: 3 CPU B 12345: 7
Write-through cache …  continued CPU B reads location 12345 from memory - loads into cache Bus 12345:3 Device I/O CPU A 12345: 3 CPU B 12345: 3
Write-through cache CPU A modifies location 12345 - write-through 12345:3 12345: 3 Cache on CPU B not updated Memory not coherent! Bus Device I/O CPU A CPU B 12345: 3 12345:0 12345: 0
Write once protocol   ,[object Object],[object Object],[object Object],[object Object],[object Object]
Write through protocol   Event   Action taken by a cache in   response to its own CPU’s operation   Action taken by a cache in response to a remote CPU’s operation  Read mis s Fetch data from memory and store in cache   no action   Read hit  Fetch data from local cache  no action   Write miss  Update data in memory and store in cache  no action   Write hit   Update memory and cache   invalidate cache entry
For example  A B W 1 C W 1 CLEAN Memory is correct ,[object Object],[object Object],[object Object],CPU A B W 1 C W 1 W 1 CLEAN CLEAN Memory is correct (b) A reades word W and gets W 1 . B does not respond to the read, but the memory  does.
A B W 1 C W 2 W 1 A B W 1 C W 3 W 1 DIRTY INVALID DIRTY INVALID Memory is correct (c)A write a value W2, B snoops on the bus, sees the write, and invalidates its entry. A’s copy is marked DIRTY. Not update memory Memory is correct (d) A write W again. This and subsequent writes by A are done locally, without any bus traffic.
A B W 1 C W 3 W 1 INVALID INVALID DIRTY W 3 (e) C reads or writes W. A sees the request by snooping on the bus, provides the value, and invalidates its own entry. C now has the only valid copy. Not update memory
Ring-Based Multiprocessors : Memnet CPU CPU CPU CPU CPU CPU CPU Private memory MMU Cache Home memory Memory management unit Location Interrupt Home Exclusive Valid 0 1 2 3 The block table
Protocol ,[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object]
Similarities b bus based and ring based multiprocessors ,[object Object],[object Object]
DIFFERENCES B TWO MULTIPROCESSORS ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
The end.

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Dos final ppt

  • 1. “ SHARED MEMORY” MADE BY: SANJANA BAKSHI 7IT087 A PPT ON
  • 2.
  • 3.
  • 4.
  • 5.
  • 6.
  • 7.
  • 8.
  • 9. Bus-based multiprocessors Bus-based multiprocessors BUS BASED MULTIPROCESSORS SMP : Symmetric Multi-Processing All CPUs connected to one bus (backplane) Memory and peripherals are accessed via shared bus. System looks the same from any processor. Bus CPU A CPU B memory Device I/O
  • 10. Bus-based multiprocessors Dealing with bus overload - add local memory CPU does I/O to cache memory - access main memory on cache miss Bus memory Device I/O CPU A cache CPU B cache
  • 11. Working with a cache CPU A reads location 12345 from memory Bus 12345:7 Device I/O CPU A 12345: 7 CPU B
  • 12. Working with a cache CPU B reads location 12345 from memory Gets old value Memory not coherent! Bus 12345:7 Device I/O CPU A 12345: 3 CPU B 12345: 7
  • 13. Write-through cache … continued CPU B reads location 12345 from memory - loads into cache Bus 12345:3 Device I/O CPU A 12345: 3 CPU B 12345: 3
  • 14. Write-through cache CPU A modifies location 12345 - write-through 12345:3 12345: 3 Cache on CPU B not updated Memory not coherent! Bus Device I/O CPU A CPU B 12345: 3 12345:0 12345: 0
  • 15.
  • 16. Write through protocol Event Action taken by a cache in response to its own CPU’s operation Action taken by a cache in response to a remote CPU’s operation Read mis s Fetch data from memory and store in cache no action Read hit Fetch data from local cache no action Write miss Update data in memory and store in cache no action Write hit Update memory and cache invalidate cache entry
  • 17.
  • 18. A B W 1 C W 2 W 1 A B W 1 C W 3 W 1 DIRTY INVALID DIRTY INVALID Memory is correct (c)A write a value W2, B snoops on the bus, sees the write, and invalidates its entry. A’s copy is marked DIRTY. Not update memory Memory is correct (d) A write W again. This and subsequent writes by A are done locally, without any bus traffic.
  • 19. A B W 1 C W 3 W 1 INVALID INVALID DIRTY W 3 (e) C reads or writes W. A sees the request by snooping on the bus, provides the value, and invalidates its own entry. C now has the only valid copy. Not update memory
  • 20. Ring-Based Multiprocessors : Memnet CPU CPU CPU CPU CPU CPU CPU Private memory MMU Cache Home memory Memory management unit Location Interrupt Home Exclusive Valid 0 1 2 3 The block table
  • 21.
  • 22.
  • 23.
  • 24.