Network on-chip for turbo decoders

CONTACT: PRAVEEN KUMAR. L (,+91 – 9791938249)
MAIL ID: sunsid1989@gmail.com, praveen@nexgenproject.com
Web: www.nexgenproject.com, www.finalyear-ieeeprojects.com
Network-on-Chip for Turbo Decoders
Abstract:
The multi-application specific instruction processor (ASIP) architecture is a promising candidate
for flexible high-throughput turbo decoders. This brief proposes a network-on-chip (NoC)
structure for multi-ASIP turbo decoders. The process of turbo decoding is studied, and the
addressing patterns for turbo codes in long term evolution (LTE) and High Speed Downlink
Packet Access (HSDPA) are analyzed. Based on this analysis, two techniques, subnetworking
and calculation sequence are proposed for reducing the complexity of the NoC. The
implementation results show that the proposed structure gives an improvement of 53% for
HSDPA and 133% for LTE in throughput/area efficiency compared with state-of-the-art NoC
solutions. The proposed architecture of this paper analysis the logic size, area and power
consumption using Xilinx 14.2.
Enhancement of the project:
Existing System:
The multi application specific instruction processor is a promising area for turbo decoders. An
effective architecture level change of MASIP is used for performance improvement.
Performance analysis and comparison. In modern wireless systems, turbo codes are widely used
for their near-Shannon performance. In various standards, their turbo codes vary mainly in three
aspects: 1.code length, 2.code generator and 3.interleaving patterns. The main issue for these
ASIP and NoC architectures is the complexity overhead and thus low efficiency compared with
dedicated decoders. So, we focus on NoC architecture which supports high throughput with low
efficiency.
Due to dramatic increase in portable and battery operated applications, lower power consumption
has become a necessity in order to prolong the battery life. We focus on NoC architecture which
supports high throughput with low efficiency. Reconfigurable computing refers to systems
incorporating some form of hardware programmability, that customizes how the hardware is
used using a number of physical control points. These control points can be changed periodically
in order to execute different applications using the same hardware.

The main issue for these ASIP and NoC architectures is the complexity overhead and thus low
efficiency compared with dedicated decoders. In this brief, we focus on the NoC architecture.
The contribution of this brief is twofold: first, turbo addressing patterns are analyzed, leading to
our proposed subnetwork-based NoC architecture and second, a novel router structure and
calculation-sequence (CALS) scheme is proposed, which supports high throughput with low
complexity. The implementation results show that the proposed NoC structure can increase the
throughput/area efficiency by 53% for HSDPA and 133% for LTE compared with existing turbo
NoC solutions.
Disadvantages:
 Low throughput
 High area and power
Proposed System:
Topology and NoC Data Format

Fig. 1. Proposed NoC architecture.
The proposed NoC architecture is shown in Fig. 1. Since the whole NoC is divided into parallel
subnetworks, RTs and WTs from ASIP must be distributed to these subnetworks. This process is
finished by DISTRIBUTORs. Each DISTRIBUTOR buffers data from ASIP ports, and sends
them to different subnetworks according to the rule which partitions memories into S groups: a
transaction will be sent to the DEST ADDR modulo S subnetwork, where DEST ADDR is the
destination memory bank address. As a memory bank receives an RT from the subnetwork, it
will send a FT back to the corresponding subnetwork. This FT will go along routers back to the
router corresponding to the reading ASIP, and then get to the ASIP through a CONVERGER
which has the reverse effect of the DISTRIBUTOR module. Both the DISTRIBUTOR and
CONVERGER are implemented by S × S crossbar switches with input buffers. These two
modules are essential for splitting the whole network into parallel subnetworks. Note that for
drawing convenience, the same ASIP blocks are shown at both the top and the bottom of the
figure.

Fig. 2. Topology of one subnetwork.
Fig. 2 gives the topology of one subnetwork with eight routers. We use a ring style topology.
Since the ASIPs will send RTs to memories and the memories will send FTs to ASIPs at the
same time, we use bidirectional connections between routers.
Fig. 3. NoC data format.

The format of NoC transactions is shown in Fig. 3. The Read/Write (RW) field indicates whether
the transaction is for reading or writing.
Router Architecture
The router architecture is shown in Fig. 4(a). An example of a subnetwork with eight routers is
given. For timing considerations, we use pipeline registers to reduce the critical path. In addition
to these registers are used for data buffering. The structure of the ASIP input pipeline registers,
ASIP output pipeline registers (AOPR), memory input pipeline registers, and memory output
pipeline registers (MOPR) is shown in Fig. 4(b). For each pipeline register module, there are two
NoC transaction registers, which accept requests in a ping-pong style. The ROUTING and
ARBITRATION (R&A) module selects data at the ports to send to other Routers and stores data
from other routers. Fig. 4(c) shows the structure of the R&A module. From considerations of
complexity and critical path, only the CALS-based priority is used in the design of the pipeline
registers. The R&A module used a fixed priority scheme.

Fig. 4. (a) Router architecture. (b) Pipeline registers module. (c) R&A module.
Advantages:
 High throughput
 Low area and power
Software implementation:

 Modelsim
 Xilinx ISE

Network on-chip for turbo decoders

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Network on-chip for turbo decoders