1. Advanced Standard Cell Routing
Project Report of EE 201A Final Course Project
Yuqian Zhang SID: 504593236
Longjia Niu SID: 304590762
Abstract—We implement an advanced standard cell router
using the OpenAccess C++ API based on previous version of
SnakeRouter implemented by Mark Gottscho and Yasmine
Badr. Enhancement of the SnakeRouter has been accomplished
in three ways: (1). A Star Maze Routing Algorithm is
implemented to substitute the original Lee’s algorithm with
supports on an extra metal layer and an extra bi-directional
type of routing. (2). Layout generator is modified to support an
extra M3 metal layer and an extra bidirectional type of wire
geometry mapping. (3). Post processor is revised regarding
shapes-merging function to pass Design Rule Check (DRC)
tests and reduce wire length. For course project metrics, the
improved version of SnakeRouter passes 25/28 LVS tests, and
17/28 DRC tests before final presentation. We make some
updates to our previous version after the presentation and get
26/28 LVS passes, and 18/28 DRC passes in our final version.
I. ROUTER BACKGROUND
The original SnakeRouter by Mark Gottscho and Yasmine
Badr is built using Lee’s Algorithms [1] and it only supports
vertical routing on metal layer 1 and horizontal routing on
metal layer 2. Before we start, we have carefully considered
different tradeoffs in typical run-time, optimality and
memory of different routing methods including Hadlock's
Algorithm [2], Soukup's Algorithm [3] and A Star
Algorithm [4]. In our Advanced Standard Cell Routing
project, we have replaced Lee’s Algorithm by A Star
Algorithm to achieve faster run-time with minimal wire
length. Also, as some harsh restrictive conditions are
introduced, two layers are not enough for successful routing.
Hence, an extra M3 metal layer is added to the project, and
an extra bidirectional type of wire geometry mapping is
implemented. Finally, post processor dealing with special
routing cases is implemented to pass as many DRC as
possible.
II. IMPLEMENTATION
The enhanced SnakeRouter consists of three major
components: (A). Maze router using A Star Algorithm. (B).
Layout generator for three layers with vertical, horizontal
and bidirectional layout mapping. (C). Post-processor for
fixing special design rule violations. The overall program
flow is depicted in Fig. 1.
Fig. 1: Advanced Standard Cell Routing Flow Chart
(A). A Star Maze Router
A cost value is introduced as an attribute to each cell and
it is the sum of current cost and future cost. Current cost is
the distance from the source to current cell in terms of the
number of cells travelled whereas future cost is the
Manhattan distance from current cell to the target cell.
Current cell starts from the source cell and moves to the
neighbor cell with lowest cost value each iteration until the
target or filled cell with same net as source and target is
reached. The resulted path will have the lowest cost moving
from source to target and ensure minimum wire length.
Some optimizations of the basic A Star Algorithm are added
to the router. Finding the cell with minimum cost within a
vector of cells can be time consuming and the worst case
time complexity is the vector size n. We use a priority queue
from Standard Template Library (STL) for Cell object to
prioritize cell with lowest cost. Popping from the front of the
queue will take constant time and inserting new neighbor
cell to the queue will take log(n) time because the priority
queue is implemented using minimum heap data structure.
To avoid the algorithm finding zigzagging alternating route,
cell comparison function for priority queue is modified to
prioritize cells with higher column number. Take Figure. 2
for example, C is the location of the current cell and both
neighboring cells at top and right of C have the same cost
which is 6(current cost of 4 + future cost of 2). The router
will pick the cell at the top as the next current cell instead of
the one on the right. Thus, wiring complexity of future
geometric mapping can be reduced.
Fig. 2: Example of A Star Algorithm
(B). Three-Layer Layout Generator
The three-layer layout generator generates an output
that corresponds to the final layout geometry. Compared
with original layout generator, some additional features
were added: (1). Bidirectional wire geometry mapping
function is implemented, so that the program is able to map
routes to layout geometry in vertical, horizontal and
bidirectional manners according to input design rule files.
(2). Minimum area rule is satisfied for the case of single
contacts, as shown in equation (B.1) and Fig. 3 (Left). (3).
Regular contacts or vias need to satisfy contact/via
extension rule, and form polygons with the wires connected
at the same time, as shown in equation (B.2) and Fig. 3
(Right).
E Contact/Via Extension Rule A Minimum Area Rule
Via_Size 2 ∗ Ext_1 max √ , 2 . 1
Via_Size 2 ∗ Ext_1 max , 2 . 2
Fig. 3: Single Contact Geometry (Left) and Regular
Via/Contact Geometry (Right)

2. (C). Post Processor
We utilize the original algorithm from SnakeRouter for
vertical and horizontal wire geometry mapping and achieve
bidirectional wire geometry mapping by the combination of
the two. In the baseline SnakeRouter, wiring of horizontal
routes on layer with horizontal routing direction is done by
iterating cells in each row from left to right and from bottom
to top row of the cell, as shown in Figure 4 (Left). It will
find a start and end cell on each row which represents the
start and end of a wire segment and draw a rectangle
oaShape. One problem we encountered is for drawing power
nets on layer that only allows horizontal wires, the
SnakeRouter will iterate each cell in the row and will not
find the end cell after finding the start power cell in that row
because the power nets are vertically routed as the Figure 4
(Right) illustrated. As a result the finished mapping will
include a number of squared shapes to represent the power
nets. In the improved SnakeRouter, we account for this
situation because the total wire length on the layer when this
situation happens is really large. A process at the end of the
post processor is added to merge all power squares in this
case and replace all of them with a clean and simple
rectangle as shown in Figure 5.
Fig. 4: Example of Algorithm for Horizontal Wire Mapping
(Left) and Example of Vertical Power Net Mapping on
Layer Allowing Only Horizontal Wires (Right)
Fig. 5: Output Cell Layout Before / After Merging Power
Squares in Post Processing
III. RESULTS
Fig. 6. Routing Contest Results
As indicated in Fig. 6, green cells are routed instances
that can pass both LVS and DRC tests, yellow cells are
those that can only pass LVS tests, while red cells indicate
failed LVS and DRC tests. Overall, our project passes
26/28 LVS tests, and 18/28 DRC tests. Our program does
perform better in terms of run-time and wire-length but
these are held back due to the extra processing time of an
extra metal layer 3. Note that this table is a little bit
different from final presentation where we have 25/28
LVS passes and 17/28 DRC passes, because we have
optimized the program structure and made some
modifications to generate keep-out region more efficiently.
IV. CONCLUSION AND POTENTIAL IMPROVEMENT
In conclusion, our improved SnakeRouter has
successfully added support for three layer with vertical,
horizontal and bidirectional wire geometry. We have also
tried to improve the run-time by replacing Lee’s Algorithm
with A Star Algorithm. And the post processor has also been
improved to take account for merging special contacts to
reduce DRC violations and merging redundant power
squares to reduce wire length. Yet, there is still room for
potential improvements on run-time and DRC performance.
Firstly, in current version, we construct the bidirectional
layout geometry by two iterations of the whole grid. One for
vertical and one for horizontal routes. A possible
improvement would be to label each cell with the route it is
connected with, then generate layout from any labeled cell
in a route until all the connected labeled cells are traversed.
As shown in Fig. 7. This improvement would take only one
iteration to finish the layout generation.
Fig. 7. Example of Faster Layout Generator
Secondly, the current post processor merges shapes from
smaller rectangles to larger rectangles, which may violate
DRC rules and introduce redundant wire length to the layout.
A more intelligent post processor may merge shapes using
polygons when needed. As shown in Figure 8, instead of
merging the two smaller rectangles to the large rectangle on
the left which may introduce extra DRC violations because
the top left part of the bigger rectangle is considered as
redundant, a smarter post processor should merge them to
the irregular polygon on the right to avoid adding more wire
length that may cause DRC violations.
Fig. 8. Example of Intelligent Shapes Merging
REFERENCES
[1] C. Y. Lee, “An algorithm for path connections and its applications”.
IRE Transactions on Electronic Computers, 1961.
[2] F. Hadlock, “Finding a maximum cut of a planar graph in polynomial
time”. SIAM Journal of Computing, vol. 4, 1975.
[3] J. Soukup, “Fast maze router”. In Proceedings of the 15th Design
Automation Conference, 1978, pp. 100-102.
[4] Hart, P. E.; Nilsson, N. J.; Raphael, B. "A Formal Basis for the
Heuristic Determination of Minimum Cost Paths". IEEE Transactions
on Systems Science and Cybernetics, SSC4 4 (2): 100–107, 1968.