Chip-to-System Thermal Co-Design

Technologies and Tools Enabling
Chip-to-System Co-Design of
Electronics

Kamal Karimanal
Cielution LLC

12/18/2012 Confidential © Cielution LLC

Agenda

Introducing Cielution LLC

Smartmobile Era & The Need for Thermally Aware
Chip-System Co Design
• Case Study

Compact Thermal Model for Thermal/System Aware
IC Design

Chip-to-System Thermal Co-Design Flow

Validation

Conclusions

Who is Cielution?


Cielution Product Pipeline
CielSpot™ CielMech™
• Package Thermal Modeling
• Thermo-Mechanical
• Package Compact Model
Analysis of Assembly
Generation
CielSpot-CTM™ o Warpage Mitigation
• Thermally Aware IC Layout o Packaging Yield
o Traditional Packages Enhancement
o 3D Stacked Assemblies o Interconnect Reliability


Cielution Services
Expertise Areas
• Thermal and
Mechanical Simulation
• Chip, Package Board
and System Level
Engineering.

Tools Expertise
• ANSYS, Icepak, Fluent,
CFX, Flotherm

Business Model
• Fixed Cost Fixed Time
Projects
• Hourly rate &
Temporary Resources


3D Stacked IC Case Study


3D Stack on interposer
Logic 2(22x16)
4 Stacked Dies(8X6)

Interposer (36x24)

Substrate (40 X 28)

All Dimensions in mm

Packaging & Cooling Scenario I

Heat Sink

Copper Heat Spreader

PCB
Package housing
3D IC stack


Power Profile Scenario I-A- Non Overlapping (total Power=32.8W)

X

Y


Temperature Distribution on the chips


Power Profile Scenario I-B: overlapping. (total Power=32.8W)

X

Y


Temperature Distribution on the chips

Temperature increased by 16% due to hot spot proximity


Packaging & Cooling Scenario II

h = 25 W/sq.m/K, Tamb=20C

Power Distribution Scenario II-A (total
Power=12.7W)

1W

1W

2W

1W 1W


Temperature Profile for II-a


Power Profile II-B (total Power=12.7W)
1W

1W

2W

1W

1W

Power Profile for II b

Temperature increased by 26% due to hot spot proximity


Summary of Hot spot proximity Study
A 3D SOC example was used to study layout implications on for steady
state temperature distribution

2 different packaging+cooling solutions were considered
• Copper lidded package with Heat sink cooling
• MC encapsulated package without heat sink
Each package+cooling scenario was subjected to 2 different sets of power
maps.
• Sparsest distribution of hot spots on active chips.
• Closest proximity of hot spots
The case with copper lidded packaging with heat sink predicted 16% higher
temperature rise when hot spots were in close proximity.

The case with MC encapsulated package without heat sink predicted 26%
higher temperature rise when hot spots were in close proximity.

The reason for this difference in sensitivity to hot spot alignment is the
better ability of the heat spreader and heat sink base to spread heat even
when hot spots were in close proximity.

Moral?
Heat distribution plays an important role in chip temperature rise.

Hot spot proximity between chips produce unintended
consequences after heterogeneous integration.
• This is a new twist which will obsolete the existing thermal
management methodologies based on ja
Predicted temperature from thermal model are highly sensitive to:
• Packaging, Heat sinking, 3D layout of stacked chips, orthotropic
nature of laminates, and interconnect arrays.

Above sensitivities can only be captured by thermal models using
3D numerical discretization.
• Spreading and t/KA resistance formulation based approaches
have inherent assumptions which tend to introduce unknown
uncertainties.

However, the fast turn around & automation needed by IC design
flow can only be addressed by effective compact models.

CielSpot for Thermal IC Package
Detailed & Compact Thermal
Modeling


CielSpot: High Level Workflow
Stack Info

Package
CielSpot™ Material Properties
Info
Automated Geometry,
Meshing & Problem Setup Automated Thermal Snapshots
& Temperature data

Intelligent Solver Controls

Solve in
Commercial
Thermal Solver

Compact Thermal
Model

Access to Model in the commercial solver’s native format


CielSpot-CTM Usage: Compact for Fast Solve Without CFD/FEA

Pmap for Chip 1
Pmap for Chip 2
Pmap for Chip 2
…
Etc…

Input Data CielSpot Pre-
characterization CielSpot CTM

Automated Thermal
Snapshots &
Temperature data


Collaborative Thermal Modeling using CielSpot™

OSAT Proprietary Details. Need Third Party Solver

Package Details &
Packaging
Org. Typical Heatsinking CielSpot
Scenarios

Package A Compact Model Library Package C

Data Cannot be
Package B Reverse Engineered

Application Proprietary Details. Don’t Need Third Party Solver

Fabless Power Map CielSpot
Customer for Each Chip CTM™


CielSpot™ Compact Model
Validation


Validation Vehicle


Validation Approach

Stack Info

Pre-Characterization
Package Compact
Info
CielSpot using Commercial Thermal Model
Thermal Solver
(ANSYS)

Pmap for Chip 1
Pmap for Chip 2
Pmap for Chip 3 CielSpot CTM Temperature Distribution (TCTM )
…
Etc…

Compare
%Error = (Tdet-TCTM )/(Tdet -Tamb )*100
Stack Info

Package Detailed FEA Thermal Temperature
CielSpot™
Info Simulation (ANSYS) Distribution (Tdet )

Power Maps on all
Chips

Layout

PMAP for 2.1.1

PMAP for 2.1.1.1

x

Y


Error histogram (for all the 1000 monitor locations

%Error (FEA Vs 3D Solver)

0.60%

0.40%

0.20%

0.00%
Probe
Location

-0.20% %Error (FEA Vs 3D Solver)

-0.40%

-0.60%

-0.80%

-1.00%


Summary
Emphasized the need for exchange
formats, compact models and effective
methodologies.
• Presented Case Study.
• Simple rules of thumb such as Rja are obsolete metrics for
distributed heat loads on monolithic Chips.
• 3D stacks & complex supply chain complicate matters even
further
Introduced CielSpot™ & CielSpot-CTM™
• Proposed Chip-to-System thermal Co-design Methodology
suited for the complex Electronics Eco-system
Validation showed that CTM can be as accurate as
detailed thermal model
• Much faster than complete CFD
o seconds for a complete stacked die with heat sink, PCB and
distributed heat loads on each chip and thousands of probe points
• Protects IP sensitive details
o Suited for system OEM+OSAT to share with Fabless IC supplier.


Chip-to-System Thermal Co-Design

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