George Chrysos, the leading architect of Intel Xeon Phi co-processor shared the new architecture details of upcoming Intel's HPC powerhouse. Designed for highly-parallel applications, Intel Xeon Phi co-processor based on Intel Mani Integrated Core architecture will deliver the combination of industry leading performance per watt with the ability to re-use the existing code and applications without necessity of re-writing them. Equipped with more than 50 cores and built using Intel's latest 22nm 3D Tri-gate transistor technology, new co-processors will be in production this year with first supercomputers from top500 list already taking advantage of this technology.

1. Intel® Xeon Phi™ coprocessor
(codename Knights Corner)
George Chrysos
Senior Principal Engineer
Hot Chips, August 28, 2012
More on Twitter @IntelITS

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3. Intel® Many Integrated Core (Intel MIC) Architecture
Targeted at highly parallel HPC workloads
• Physics, Chemistry, Biology, Financial Services
Power efficient cores, support for parallelism
• Cores: less speculation, threads, wider SIMD
• Scalability: high BW on die interconnect and memory
General Purpose Programming Environment
• Runs Linux (full service, open source OS)
• Runs applications written in Fortran, C, C++, …
• Supports X86 memory model, IEEE 754
• x86 collateral (libraries, compilers, Intel® VTune™ debuggers, etc)
3 Visual and Parallel Computing Group Copyright © 2012 Intel Corporation. All rights reserved.

4. Knights Corner Coprocessor
KNC Card
KNC Card
TCP/IP
PC e x16
GDDR5
Channel … GDDR5
Channel
Intel® Xeon®
Processor PCIe x16
Channel
GDDR5
KN50 Cores
>
…
KN
Linux OS
Channel
GDDR5
System Memory
GDDR5
Channel … GDDR5
Channel
>= 8GB GDDR5 memory
4 Visual and Parallel Computing Group Copyright © 2012 Intel Corporation. All rights reserved.

5. Knights Corner – Power Efficient
Performance per Watt of a prototype Knights Corner Cluster
compared to the 2 Top Graphics Accelerated Clusters
1381 1380
1266
1400
1200
MFLOPS/Watt
1000
800
600
+ + +
400
200
0
Intel Corp Nagasaki Univ. Barcelona
Supercomputing Center
Knights Corner ATI Radeon Nvidia Tesla 2090
Higher is Better Source: www.green500.org
Top500 #150 Top500 #456 Top500 #177
72.9 kW 47 kW 81.5 kW
5 Visual and Parallel Computing Group Copyright © 2012 Intel Corporation. All rights reserved.

6. Knights Corner Micro-architecture
Core Core Core Core
PCIe
Client L2 L2 L2 L2
Logic
GDDR MC TD TD TD TD GDDR MC
GDDR MC GDDR MC
TD TD TD TD
L2 L2 L2 L2
Core Core Core Core
6 Visual and Parallel Computing Group Copyright © 2012 Intel Corporation. All rights reserved.

7. Knights Corner Core
PPF PF D0 D1 D2 E WB
T0 IP
T1 IP L1 TLB Code Cache Miss
T2 IP and 32KB
T3 IP
Code Cache TLB Miss
16B/Cycle (2 IPC)
4 Threads
In-Order Decode uCode 512KB
TLB Miss HWP
L2 Cache
Handler
Pipe 0 Pipe 1 L2 Ctl
L2 TLB
VPU RF X87 RF Scalar RF
VPU
X87 ALU 0 ALU 1 To On-Die Interconnect
512b SIMD TLB Miss
L1 TLB and 32KB Data Cache
DCache Miss
Core
X86 specific logic < 2% of core + L2 area
7 Visual and Parallel Computing Group Copyright © 2012 Intel Corporation. All rights reserved.

8. Vector Processing Unit
PPF PF D0 D1 D2 E WB
D2 E VC1 VC2 V1-V4 WB
D2 E VC1 VC2 V1 V2 V3 V4
VPU LD
DEC RF
3R, 1W Vector ALUs
EMU
16 Wide x 32 bit
ST 8 Wide x 64 bit
Fused Multiply Add
Mask Scatter
RF Gather
8 Visual and Parallel Computing Group Copyright © 2012 Intel Corporation. All rights reserved.

9. Interconnect
BL - 64 Bytes Data
Core Core Core Core
L2 L2 L2 L2
AD Command and Address
AK Coherence and Credits
TD TD TD TD
TD TD TD TD
AK
AD
L2 L2 L2 L2
Core Core Core Core
BL – 64 Bytes
9 Visual and Parallel Computing Group Copyright © 2012 Intel Corporation. All rights reserved.

10. Distributed Tag Directories
Core Core Core Core
L2 L2 L2 L2 TAG Core Valid Mask State
TAG Core Valid Mask State
TD TD TD TD
TD TD TD TD
L2 L2 L2 L2 Tag Directories track cache-lines in all L2s
Core Core Core Core
10 Visual and Parallel Computing Group Copyright © 2012 Intel Corporation. All rights reserved.

11. Interleaved Memory Access
Core Core
GDDR MC
L2 L2
TD TD
Core
GDDR MC
L2
TD
Core
Core
L2
TD
L2
TD
Core
GDDR MC
TD
L2
TD TD
GDDR MC
L2 L2
Core Core
11 Visual and Parallel Computing Group Copyright © 2012 Intel Corporation. All rights reserved.

12. Interconnect: 2X AD/AK
BL - 64 Bytes
Core Core Core Core
L2 L2 L2 L2
AD
AK
TD TD TD TD
2x
TD TD TD TD
AK
AD
L2 L2 L2 L2
Core Core Core Core
BL – 64 Bytes
12 Visual and Parallel Computing Group Copyright © 2012 Intel Corporation. All rights reserved.

13. Multi-threaded Triad – Saturation for 1 AD/AK Ring
Performance
Simulation Data indicates
saturation for a single
AD/AK ring
0 5 10 15 20 25 30 35 40 45 50
Cores Running
Results measured in development labs at Intel on Knights Corner prototype hardware and systems. For more information go to http://www.intel.com/performance
13 Visual and Parallel Computing Group Copyright © 2012 Intel Corporation. All rights reserved.

14. Multi-threaded Triad – Benefit of Doubling AD/AK
Silicon Data for
2 AD + AK rings > 40%
Performance
Simulation Data indicates
saturation for a single
AD/AK ring
0 5 10 15 20 25 30 35 40 45 50
Cores Running
Results measured in development labs at Intel on Knights Corner prototype hardware and systems. For more information go to http://www.intel.com/performance
14 Visual and Parallel Computing Group Copyright © 2012 Intel Corporation. All rights reserved.

15. Streaming Stores
Streams Triad
for (i=0; i<HUGE; i++)
A[i] = k*B[i] + C[i];
Without Streaming Stores
Read A, B, C, Write A
256 Bytes transferred to/from memory per iteration
With Streaming Stores
Read B, C, Write A
192 Bytes transferred to/from memory per iteration
15 Visual and Parallel Computing Group Copyright © 2012 Intel Corporation. All rights reserved.

16. Multi-threaded Triad — with Streaming Stores
Silicon Data
Streaming Stores > 30%
Performance
0 5 10 15 20 25 30 35 40 45 50
Cores Running
Results measured in development labs at Intel on Knights Corner prototype hardware and systems. For more information go to http://www.intel.com/performance
16 Visual and Parallel Computing Group Copyright © 2012 Intel Corporation. All rights reserved.

17. Cache Hierarchy Micro-architecture Choices
L2 TLB
64 entry, holds PTEs and PDEs vs. no L2 TLB
Dcache Capability
Simultaneous 512b load and 512b store vs. 1 load or store per cycle
L2 Cache
512 KB vs. 256 KB
Hardware Prefetcher
16 stream detectors, prefetch into the L2 vs. no HWP (rely only on software prefetching)
17 Visual and Parallel Computing Group Copyright © 2012 Intel Corporation. All rights reserved.

18. Per-Core ST Performance Improvement (per cycle)
Spec FP 2006
3.0
Performance impact of KNC core uArch improvements
2.5
2.0
1.5
1.0
0.5
0.0
>1.8x Average Performance/Cycle Improvement – 1 Core, 1 Thread
Results measured in development labs at Intel on Knights Corner and Knights Ferry prototype hardware and systems. For more information go to http://www.intel.com/performance
18 Visual and Parallel Computing Group Copyright © 2012 Intel Corporation. All rights reserved.

19. Caches – For or Against?
Relative BW Relative BW/Watt
50
45
40 Caches:
35  high data BW
30  low energy per byte of data supplied
25  programmer friendly (coherence just works)
20
15
10
5
0
Memory BW L2 Cache BW L1 Cache BW
Coherent Caches are a key MIC Architecture Advantage
Results have been simulated and are provided for informational purposes only. Results were derived using simulations run on an architecture simulator or model. Any difference in system hardware or software design or configuration may affect actual performance.
19 Visual and Parallel Computing Group Copyright © 2012 Intel Corporation. All rights reserved.

20. Example: Stencils
spatial time-step simulation of a physical system
L2$
Sized
Cache blocking promotes much higher performance
and performance/watt vs. memory streaming
20 Visual and Parallel Computing Group Copyright © 2012 Intel Corporation. All rights reserved.

21. Power Management: All On and Running
PCIe IO
Core Core Core Core
PCIe
Client L2 L2 L2 L2
Logic
GDDR5 GDDR5
GDDR5 GDDR5
GDDR IO
TD TD TD TD
GDDR IO
GDDR MC GDDR MC
GDDR5 GDDR5
GDDR MC GDDR MC
TD TD TD TD
GDDR5 GDDR5
GDDR5 GDDR5
L2 L2 L2 L2
Core Core Core Core
21 Visual and Parallel Computing Group Copyright © 2012 Intel Corporation. All rights reserved.

22. Core C1: Clock Gate Core
PCIe IO
Core Core Core Core
PCIe
Client L2 L2 L2 L2
Logic
GDDR5 GDDR5
GDDR5 GDDR5
GDDR IO
TD TD TD TD
GDDR IO
GDDR MC GDDR MC
GDDR5 GDDR5
GDDR MC GDDR MC
TD TD TD TD
GDDR5 GDDR5
GDDR5 GDDR5
L2 L2 L2 L2
Core Core Core Core
When all 4T on a core have halted, core clock gates itself
22 Visual and Parallel Computing Group Copyright © 2012 Intel Corporation. All rights reserved.

23. Core C6: Power Gate Core
PCIe IO
Core Core Core Core
PCIe
Client L2 L2 L2 L2
Logic
GDDR5 GDDR5
GDDR5 GDDR5
GDDR IO
TD TD TD TD
GDDR IO
GDDR MC GDDR MC
GDDR5 GDDR5
GDDR MC GDDR MC
TD TD TD TD
GDDR5 GDDR5
GDDR5 GDDR5
L2 L2 L2 L2
Core Core Core Core
C1 time-out, power gate core, save leakage, requires core-re-init
23 Visual and Parallel Computing Group Copyright © 2012 Intel Corporation. All rights reserved.

24. Package Auto C3
PCIe IO
Core Core Core Core
PCIe
Client L2 L2 L2 L2
Logic
GDDR5 GDDR5
GDDR5 GDDR5
GDDR IO
TD TD TD TD
GDDR IO
GDDR MC GDDR MC
GDDR5 GDDR5
GDDR MC GDDR MC
TD TD TD TD
GDDR5 GDDR5
GDDR5 GDDR5
L2 L2 L2 L2
Core Core Core Core
Timeout when all cores have been in C6,
clock gate the L2 and interconnect
24 Visual and Parallel Computing Group Copyright © 2012 Intel Corporation. All rights reserved.

25. Package C6
PCIe IO
Core Core Core Core
PCIe
Client L2 L2 L2 L2
Logic
GDDR5 GDDR5
GDDR5 GDDR5
GDDR IO
TD TD TD TD
GDDR IO
GDDR MC GDDR MC
GDDR5 GDDR5
GDDR MC GDDR MC
TD TD TD TD
GDDR5 GDDR5
GDDR5 GDDR5
L2 L2 L2 L2
Core Core Core Core
Host Driver can initiate Package C6 –
Uncore Voltage Off, requires partial restart
25 Visual and Parallel Computing Group Copyright © 2012 Intel Corporation. All rights reserved.

26. Summary
Intel® Xeon Phi™ coprocessor provides:
Performance and Performance/Watt for highly parallel HPC
with cores, threads, wide-SIMD, caches, memory BW
Intel Architecture
general purpose programming environment
advanced power management technology
KNC delivers programmability and performance/watt for highly parallel HPC
26 Visual and Parallel Computing Group Copyright © 2012 Intel Corporation. All rights reserved.

27. Thank You
Knights Corner brought to you by:
IAG (Intel Architecture Group)
• DCSG (Data Center and Systems Group)
• VPG (Visual and Parallel Group) MIC
– HW Architecture
– HW Design
– SW
SSG (Software and Services Group) MIC
IL PCL (Intel Labs – Parallel Computing Lab)
27 Visual and Parallel Computing Group Copyright © 2012 Intel Corporation. All rights reserved.

29. Vector Processor: 512b SIMD Width
SP SP SP SP
15
DP7
11
DP5
7
DP3
3
DP1
Shared Multiplier
SP SP SP SP Circuit for SP/DP
14 10 6 2
SP SP SP SP
13 9 5 1
DP6 DP4 DP2 DP0
SP SP SP SP
12 8 4 0
RF3 RF2 RF1 RF0
16 wide SP SIMD, 8 wide DP SIMD
2:1 Ratio good for circuit optimization
29 Visual and Parallel Computing Group Copyright © 2012 Intel Corporation. All rights reserved.

30. Gather/Scatter Address Machinery
Gather Instruction Loop
gather-prime
loop: gather-step; jump-mask-not-zero loop Vector Register
Index0 Index1 Index2 Index3 Index4 Index5 Index6 Index7
Scalar Register
Base Address
+ + + + + + + +
Mask Register
Addr0 Addr1 Addr2 Addr3 Addr4 Addr5 Addr6 Addr7
1 1 1 1 1 1 1 1
Clear
Find
First
To TLB/
Access Address DCACHE
Clear = =
Gather/Scatter machine takes advantage
of cache-line locality
30 Visual and Parallel Computing Group Copyright © 2012 Intel Corporation. All rights reserved.

31. Package Deep C3
PCIe IO
Core Core Core Core
PCIe
Client L2 L2 L2 L2
Logic
GDDR5 GDDR5
GDDR5 GDDR5
GDDR IO
TD TD TD TD
GDDR IO
GDDR MC GDDR MC
GDDR5 GDDR5
GDDR MC GDDR MC
TD TD TD TD
GDDR5 GDDR5
GDDR5 GDDR5
L2 L2 L2 L2
Core Core Core Core
Host Driver Initiated – L2/Ring/TDs dropped
to retention V, memory in self refresh
31 Visual and Parallel Computing Group Copyright © 2012 Intel Corporation. All rights reserved.