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A Scalable and Modular Architecture for High-Performance
Packet Classification
Abstract
Packet classification is widely used as a core function for various applications in network
infrastructure. With increasing demands in throughput, performing wire-speed packet
classification has become challenging. Also the performance of today's packet classification
solutions depends on the characteristics of rulesets. In this work, we propose a novel modular
Bit-Vector (BV) based architecture to perform high-speed packet classification on Field
Programmable Gate Array (FPGA). We introduce an algorithm named StrideBV and modularize
the BV architecture to achieve better scalability than traditional BV methods. Further, we
incorporate range search in our architecture to eliminate ruleset expansion caused by range-to-prefix
conversion. The post place-and-route results of our implementation on a state-of-the-art
FPGA show that the proposed architecture is able to operate at 100+ Gbps for minimum size
packets while supporting large rulesets up to 28 K rules using only the on-chip memory
resources. Our solution is ruleset-feature independent , i.e. the above performance can be
guaranteed for any ruleset regardless the composition of the ruleset.
Existing System
Packet classification is widely used as a core function for various applications in network
infrastructure. With increasing demands in throughput, performing wire-speed packet
classification has become challenging. Also the performance of today's packet classification
solutions depends on the characteristics of rulesets.

2. Proposed System
we propose a novel modular Bit-Vector (BV) based architecture to perform high-speed packet
classification on Field Programmable Gate Array (FPGA). We introduce an algorithm named
StrideBV and modularize the BV architecture to achieve better scalability than traditional BV
methods. Further, we incorporate range search in our architecture to eliminate ruleset expansion
caused by range-to-prefix conversion. The post place-and-route results of our implementation on
a state-of-the-art FPGA show that the proposed architecture is able to operate at 100+ Gbps for
minimum size packets while supporting large rulesets up to 28 K rules using only the on-chip
memory resources. Our solution is ruleset-feature independent , i.e. the above performance can
be guaranteed for any ruleset regardless the composition of the ruleset.
System Configuration:-
Hardware Configuration:-
 Processor - Pentium –IV
 Speed - 1.1 Ghz
 RAM - 256 MB(min)
 Hard Disk - 20 GB
 Key Board - Standard Windows Keyboard
 Mouse - Two or Three Button Mouse
 Monitor - SVGA

3. Software Configuration:-
 Operating System : Windows XP
 Programming Language : JAVA
 Java Version : JDK 1.6 & above.