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BUILT IN TEST (BIT) EFFECTIVENESS

BIT Effectiveness Defined

BIT Effectiveness (BITEFF) is the probability of obtaining the correct operational
status of the Controller using BIT during the mission phase of the aircraft. It is a
function of:
a)    Total Controller Failure Rate
b)    Fault Detection Capability
c)    False Alarm Probability
d)    The operating time (T) required to conduct BIT




BITEFF =         e − FR1.T .(1+ FAP)  +  FDC .1 − e − FR1.T .(1+ FAP) 
                 
                                      1 + FAP  
                                                                       
                                                                           


                                                              FDC     Where:
  Minimum (Worst Case, when T → ∞ ) BITEFF =
                                                           (1 + FAP ) FDC = Fault Detection Capability
                                                                       FAP = False Alarm Probability



             FRD             Where:
  FDC =                      FRD = BIT Detectable Controller Failure Rate
             FR1             FR 1 = Total Controller Failure Rate



             FRFA       Where:
  FAP =                 FRFA = BIT False Alarm Rate, Note 1
              FR2       FR 2 = FR1 - (Failure Rate of BIT Circuitry)

                        Note 1: The prediction or measurement of False Alarm Rate is very
                              difficult. Design steps have to be taken to reduce False Alarm
                              Rate



Fault Detection Capability (FDC) Requirement ?
False Alarm Rate Requirement ?
                                                                            Customer
                                                                            Specified




Hilaire Perera
The percent of false alarms is a difficult parameter to measure accurately
because an initial fault detection followed by an analysis indicating that no fault
exists can signify several different occurrences, such as:

•     The BIT system erroneously detected a fault.
•     An intermittent out-of-tolerance condition exists ….. somewhere
•     A failure exists but cannot be readily reproduced in a maintenance
      environment

The percent of false removals can be a more difficult problem to address. False
removals may be caused by:

•     Incorrect BIT logic.
•     Wiring or connection problems which manifest themselves as faulty
      equipment
•     Improper match of tolerances between the BIT and test equipment at the next
      higher maintenance level

The resolution of each type of false alarm and false removal requires a
substantially different response. From a logistic viewpoint, false alarms often
lead to false removals creating unnecessary demands on supply and
maintenance systems. Of potentially more concern is the fact that false alarms
and removals create a lack of confidence in the BIT system to the point where
maintenance or operations personnel may ignore fault detection indications.

                            BUILT IN TEST (BIT) EFFECTIVENESS
                                         Example

                     −6
    FR1 := 42 ⋅ 10                Total CS Failure Rate (Failures/Hour)

    FAP := 0.01                   False Alarm Probability

    FDC := .99                    Fault Detection Capability

    T := 30                       Operating Time (Hours) Required to conduct BIT


                      − [ FR1 ⋅ T ⋅ ( 1+ FAP) ]       FDC                   − [ FR1 ⋅ T ⋅ ( 1+ FAP) ]
      BITEFF := e
                                                  +  ( 1 + FAP )  ⋅ 1 − e
                                                                                                       
                                                                   
        BITEFF = 0.999975

       −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

    FAP := 0.20                   False Alarm Probability

                     − [ FR1 ⋅ T ⋅ ( 1+ FAP) ]   FDC                   − [ FR1 ⋅ T ⋅ ( 1+ FAP) ]
     BITEFF := e
                                             +  ( 1 + FAP )  ⋅ 1 − e
                                                                                                  
                                                              
       BITEFF = 0.999736


Hilaire Perera

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Bit effectiveness

  • 1. BUILT IN TEST (BIT) EFFECTIVENESS BIT Effectiveness Defined BIT Effectiveness (BITEFF) is the probability of obtaining the correct operational status of the Controller using BIT during the mission phase of the aircraft. It is a function of: a) Total Controller Failure Rate b) Fault Detection Capability c) False Alarm Probability d) The operating time (T) required to conduct BIT BITEFF = e − FR1.T .(1+ FAP)  +  FDC .1 − e − FR1.T .(1+ FAP)     1 + FAP        FDC Where: Minimum (Worst Case, when T → ∞ ) BITEFF = (1 + FAP ) FDC = Fault Detection Capability FAP = False Alarm Probability FRD Where: FDC = FRD = BIT Detectable Controller Failure Rate FR1 FR 1 = Total Controller Failure Rate FRFA Where: FAP = FRFA = BIT False Alarm Rate, Note 1 FR2 FR 2 = FR1 - (Failure Rate of BIT Circuitry) Note 1: The prediction or measurement of False Alarm Rate is very difficult. Design steps have to be taken to reduce False Alarm Rate Fault Detection Capability (FDC) Requirement ? False Alarm Rate Requirement ? Customer Specified Hilaire Perera
  • 2. The percent of false alarms is a difficult parameter to measure accurately because an initial fault detection followed by an analysis indicating that no fault exists can signify several different occurrences, such as: • The BIT system erroneously detected a fault. • An intermittent out-of-tolerance condition exists ….. somewhere • A failure exists but cannot be readily reproduced in a maintenance environment The percent of false removals can be a more difficult problem to address. False removals may be caused by: • Incorrect BIT logic. • Wiring or connection problems which manifest themselves as faulty equipment • Improper match of tolerances between the BIT and test equipment at the next higher maintenance level The resolution of each type of false alarm and false removal requires a substantially different response. From a logistic viewpoint, false alarms often lead to false removals creating unnecessary demands on supply and maintenance systems. Of potentially more concern is the fact that false alarms and removals create a lack of confidence in the BIT system to the point where maintenance or operations personnel may ignore fault detection indications. BUILT IN TEST (BIT) EFFECTIVENESS Example −6 FR1 := 42 ⋅ 10 Total CS Failure Rate (Failures/Hour) FAP := 0.01 False Alarm Probability FDC := .99 Fault Detection Capability T := 30 Operating Time (Hours) Required to conduct BIT − [ FR1 ⋅ T ⋅ ( 1+ FAP) ]  FDC  − [ FR1 ⋅ T ⋅ ( 1+ FAP) ] BITEFF := e   +  ( 1 + FAP )  ⋅ 1 − e     BITEFF = 0.999975 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− FAP := 0.20 False Alarm Probability − [ FR1 ⋅ T ⋅ ( 1+ FAP) ]  FDC  − [ FR1 ⋅ T ⋅ ( 1+ FAP) ] BITEFF := e   +  ( 1 + FAP )  ⋅ 1 − e     BITEFF = 0.999736 Hilaire Perera