1. DARPA SBIR/STTR Phase II Project Description
Highly Integrated Silicon Based RF Electronics
Distribution Statement A: Approved for Public Release; – Distribution is unlimited Page 1
Company Web Site URL: www.advtecheng.org
Point of Contact Name: Frank Lucchesi
Phone Number: 952-465-6009 Email: F.Lucchesi@AdvTechEng.com
DARPA Topic Number/Title: Highly Integrated Silicon Based RF Electronics / SB082-044
DARPA Project Contract Number: W91-W91CRB-10-C-0078
Phase II SBIR/STTR Project Period of Performance: 26 April 2010 - 25 June 2012
Technical challenge being addressed: Achieve unprecedented levels of integration for highly complex RF
microwave, mm-wave and analog/digital/mixed-signal modules using Silicon Complementary Metal Oxide
Semiconductor (CMOS) technology to support emerging DoD-critical applications such as wafer-scale phase array
mono-static radars, bi-static radars, MIMO radars, direction finding (DF) signals intelligence (SIGINT), highly-
integrated electronic warfare systems, or compact sensing systems
Prototype Description: Wide bandwidth, Ka-band, Si-based Transmit/Receive (T/R) integrated circuits (ICs) in a
form factor less than 7 mm
2
, comprising a T/R module that can be placed immediately behind each radiating
element, in much higher numbers than are currently realized. Today’s systems use discrete III-V semiconductor
components that consume more power and are more costly to manufacture. ATEI’s level of silicon integration, the
critical circuits of which were demonstrated in Phase II, can completely transform the design approach of AESA
based systems including MIMO radar, digital radar, communications and electronic combat systems (see these and
other applications below).
Prototype Availability Date and Projected Technology Readiness Level (TRL) and Manufacturing Readiness Level
(MRL): Critical Transmit and Receive circuit blocks - TRL: ~ 4-5 (demo/tested July 2012). Table 1 below shows the
allocated circuit block requirements and associated test results for critical RF front end RFIC circuit blocks. The
prototype results exceeds our expectations and satisfies the first step to fully validate the highly integrated RF
front end architecture for AESA MMW and MIMO radar implementation; The associated 8HP SiGe process MRL 9;
TRL of the complete MIMO radar RFFE Architecture: 3-4.
Table 1 - Critical or Key 28-30 GHz RFIC Circuit Blocks Simulated, Fabricated and Tested
Manufacturing Innovation (Technology and Processes)/Challenges being addressed: The MRL for the IBM 8HP
SiGe IC fabrication process used in ATEI’s Phase II project is 9
Potential Markets/Operational environments/Applications/End-users: missile RF Seekers; missile forward/side
looking fuse; surveillance radar; tactical radar; digital radar; MIMO radar; electronic warfare system; information
operations systems; bi-static radar; UAS or RPA sense and avoid RF sensor; RF data links; SIGINT systems;
information warfare systems; satellite mono-static or multi-static RF sensors; low visibility precision landing
sensors; compact sensing systems. Other applications include domestic RPA sense and avoid system; compact
automobile sense and avoid; high frequency WiMax; ground portable high resolution radar; unattended ground
sensor; compact sensing systems.
Systems Integration: ATEI's technology is applicable to many platforms and sponsors. These include: (1) advanced
low cost MMW radar seekers: JAGM - future upgrades, CTMS Transceiver, Small Diameter Bomb, missile or dumb
bomb fuzes; (2) advanced AESA Radars & Seekers: SM II(x), SM V(x), Tomahawk Blk IVA MMW seeker, Extended
NATO Sea Sparrow, Fighter Radars, Surveillance Radars, Tactical Radars, and UAS RF Payloads; and (3) advanced
communication: SM III Block 2/b, UAS communications. Other opportunities include: F/A-35 Joint Strike Fighter –
spec test chip perf. spec test chip perf. units
Gain 30 32.4 10 6 dB
NF 3.5 3.45 15 5 ±1.5 dB
IP1dB -30 -26.6 -5 +1 dBm
IIP3 -20 -18 5 14 dBm
S11 < -10 -15 < -10 -20.2 dB
S22 < -10 -13.5 < -10 -15.8 dB
Parameter
High Gain Low Gain
Rx RF Front-End 2 stage LNA
PA Parameter Spec / Goal
Simulated
Test Chip Perf
Measured units
Output 1 dBCP 15 (20) 14.8 17 dBm
OIP3 25 (30) 27.5 31.7 dBm
S11 < -10 -17 -30 dB
S22 < -10 -15 -15 dB
Power Amplifier Variant 2

2. DARPA SBIR/STTR Phase II Project Description
Highly Integrated Silicon Based RF Electronics
Distribution Statement A: Approved for Public Release; – Distribution is unlimited Page 2
SIGINT pod - direct conversion receiver, RPA/UAS RF radar payloads; RPA/UAS sense and avoid radar; GPS denied
and or navigational aid; LPD/LPI data links; ground based radars; airborne tactical radars
Advantages/Value: Actively Electronic Scanned Arrays (AESA) based systems use semiconductor-based
transmit/receive modules for their circuits. These systems have relied on numerous III-V MMICs and discrete
components for RF and base-band sections. Each of these blocks requires their own peripheral circuits and
numerous interfaces that drives overall array cost, size, weight and power (CSW&P). In addition, the required
transmit power per element are on the order of 10’s of Watts depending on operational frequency and range
requirements, driving the need for new or exotic materials and high performance cooling solutions to address
higher output power amplifiers and increasing LNA dissipation. The advantage of ATEI's highly integrated silicon
based RF electronics solution is that is collapses the entire RF front-end electronics consisting of numerous discrete
MMIC components, ancillary peripheral circuits, modules/boards, and associated interfaces into a single RF
integrated circuit or chip (RFIC). The elimination of numerous analog components, ancillary circuits, and associated
interfaces per element results in significant (> 10x) reductions in cost, size, weight and power (CSW& P). The single
RFIC solution also improves performance through the elimination of numerous discrete component and interfaces
which contributes to channel loss, gain variation and phase errors. This also has the added benefit of removing
additional discrete components that would be otherwise be required to calibrate out gain and phase imbalances.
The elimination of numerous discrete components and reducing the overall footprint of the T/R module ensures
on-grid integration with array elements which eliminates the need for a dilation layer between the array elements
and T/R module. This further improves CSW&P and performance by reducing transmit loss and noise figure
(improved sensitivity), respectively.
Technical and Manufacturing Risk and Mitigation: ATEI has developed an effective process to systematically
review and audit the quality of the ICs described above and daily support operations to meet customer/contract
requirements . As part of this process, we identify the required elements of each task, as well as the capabilities
necessary to perform the task, and ensure the availability of the resources required to support each task at the
highest possible standard. Each project team and all team personnel are periodically reviewed to ensure that
technical requirements and quality assurance objectives are met, with no decline in quality or performance at any
level.
Research and Development (R&D) Road Map Overview: To complete development of an RFIC T/R module for a
prototype Ka-band seeker (Tomahawk Block IV+, for example), the cost is estimated to be approx. $3M over 24
months. This activity would include transitioning circuit blocks to an actual transition platform architecture, RFIC
design, fabrication, and testing. The estimated cost reduction is approx. 30% to 50% per array element. To
perform a complete system analysis and optimally design transmit and receive circuit blocks to the new system-
level specs, including 2 fabrication spins, the design and characterization of a fully integrated Ka band transceiver
are estimated to cost approximately $5M - $6.5M over 36 months to complete.
Business model(s): Professional services; in-house system/subsystem concept, design and development;
licensing; manufacturing/fabrication.
Company Business Readiness: Since 2008, ATEI’s management and technical team has been providing advanced
technology products and services to government and industry customers with the highest business ethics and
technical standards. ATEI implements various policies, plans and procedures which include: ATEI Company Policy,
ATEI System Security Plan, ATEI Security Standard Practice Procedures and ATEI Information Security Profile. ATEI
has successfully passed government accounting and annual defense security audits by the DCAA and Defense
Security Service (DSS), respectively.
The views expressed are those of the author and do not reflect the official policy or position of the Department
of Defense or the U.S. Government.
_____________________________________________________________________________________