This document presents a physical model for nitride-trapping non-volatile memories with a tri-gate structure. The model simulates Fowler-Nordheim tunneling during write/erase operations using a 1D approach that accounts for planar and corner regions. Experimental data from fabricated tri-gate SONOS and THiONOS devices matches the model's predictions for programming window, width dependence, and temperature effects. The model indicates corners will have a greater impact on charge trapping at smaller dimensions, and scaling to high-density cell sizes could enable faster write dynamics.