1. Computer Arithmetic
 Prepared by:
 Buddha Shrestha
 Devendra Bhandari
 Diasy Dongol

2. • Arithmetic means the operation with operand.
– Like
• ADDITION ( + )
• SUBTRACTION ( - )
• MULTIPLICATION ( * )
• DIVIDE ( / )

3. Eight Conditions for Signed-
Magnitude Addition/Subtraction
Operation
ADD
Magnitudes
SUBTRACT Magnitudes
A > B A < B A = B
(+A) + (+B) + (A + B)
(+A) + (-B) + (A – B ) - (B – A ) + (A – B )
(-A) + (+B) - (A – B ) + (B – A ) + (A – B )
(-A) + (-B) - ( A + B)
(+A) - (+B) + (A – B ) - (B – A ) + (A – B )
(+A) - (-B) + (A + B)
(-A) - (+B) - ( A + B)
(-A) - (-B) - (A – B ) + (B – A ) + (A – B )
1
2
3
4
5
6
7
8

4. Hardware for signed-magnitude
addition and subtraction
A register
AVF
E
Bs
AS
B register
Complementer
Parallel Adder
S
Load Sum
M
Mode Control
Input Carry
Output
Carry

6. Add
operation
≠ 0 =0
A>=B
As = BS
=0=1
Augend in A
Added in B
END
As BS+
EA A + B
AVF E
EA A + B +1
AVF 0
E
A
As 0
A A
A A+1
As As
As ≠
BS
=0 =1
A<B

7. • For Example of Addition
• (+1) + (+2)
(+A) + (+B)

8. Add
operation
≠ 0 =0
A>=B
As = BS
=0=1
Augend in A
Added in B
END
As BS+
EA A + B
AVF E
EA A + B +1
AVF 0
E
A
As 0
A A
A A+1
As As
As ≠ BS
=0 =1
A<B

9. • (-1) + (+2)
(-A) + (+B)

10. Add
operation
≠ 0 =0
A>=B
As = BS
=0=1
Augend in A
Added in B
END
As BS+
EA A + B
AVF E
EA A + B +1
AVF 0
E
A
As 0
A A
A A+1
As As
As ≠ BS
=0 =1
A<B

11. • For Example of Subtraction
• (+1) - (-2)
(+A) - (-B)

12. As ≠ BS
Subtract
operation
≠ 0 =0
A>=B
As = BS
=0 =1
Miuend in A
Subtrahend in B
END
As BS+
EA A + B
AVF E
EA A + B +1
AVF 0
E
A
As 0
A A
A A+1
As As
=0 =1
A<B

13. • (+5) – (+2)
(+A) – (+B)

14. As ≠ BS
Subtract
operation
≠ 0 =0
A>=B
As = BS
=0 =1
Miuend in A
Subtrahend in B
END
As BS+
EA A + B
AVF E
EA A + B +1
AVF 0
E
A
As 0
A A
A A+1
As As
=0 =1
A<B

15. Figure: Hardware for signed-2’s
complement addition and subtraction.
BR register
Complementer and
parallel adder
AC register
V
Overflow

16. Subtract
Figure: Algorithm for adding and subtracting numbers
in signed-2’s complement representation.
Add
Augend in AC
Addend in BR
AC AC + BR
V overflow
END
Minuend in AC
Subtrahend in BR
AC AC + BR + 1
V overflow
END

17. Figure: Hardware for multiply operation
Bs
B register Sequence counter (SC)
Complementer
and parallel adder
A register Q register
As
E
Qs
(rightmost bit)
Qn
0

18. SC
Qn
Multiply operation
Multiplicand in B
Multiplier in Q
As Qs Bs
Qs Qs Bs
A 0,E 0
SC n-1
EA A + Bshr EAQ
SC SC-1
END
(products is in AQ)
= 0
= 0 = 1
≠ 0
Figure: Flowchart for multiply operation.

19. BOOTH MULTIPLICATION
ALGORITHM
 Introduction
 Hardware for Booth Algorithm
 Booth Algorithm for multiplication of signed 2’s
complement numbers

20. INTRODUCTION
 multiplication algorithm that multiplies two
signed binary numbers in two's complement
notation.
 was invented by Andrew Donald Booth in 1950
 used desk calculators that were faster
at shifting than adding and created the algorithm to
increase their speed
is of interest in the study of computer architecture.

21. Hardware for Booth Algorithm
Sign bits are not separated
from the rest of the
registers
rename registers A,B, and
Q as AC,BR and QR
respectively
Qn designates the least
significant bit of the
multiplier in register QR
Flip-flop Qn+1 is appended
to QR to facilitate a double
bit inspection of the
multiplier
BR register Sequence COUNTER
(SC)
Complementer and
parallel adder
AC register QR register
Qn Qn+1

22. Booth Algorithm for
multiplication of signed 2’s
complement numbers

23. = 10
=00
=11
Multiplicand in BR
Multiplier in QR
AC<-0
Qn+1<-0
SC<-n
Qn
Qn+1
AC<-AC+BR+1 AC<-AC+BR
ASHR(AC & QR)
SC<-SC-1
SC END
Multiply
≠ 0 = 0
= 01