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Introducing SD 4.0 Device
Controller
              By Dennis McCarty




  ©Arasan Chip Systems Inc. 2011
Arasan Chip Systems Total IP Solutions
SD 4.0 Improvements
Core Architecture
Deliverables
Arasan Advantages




           ©Arasan Chip Systems Inc. 2011
Arasan Total IP Solutions




©Arasan Chip Systems Inc. 2011
SD 4.0 Background

UHS-II PHY for faster throughput
  • 1.56 GB/s/lane at 52MHz
  • 300 MB/s overall
Differential signaling
  • D0+/- and D1+/-
Bus clock 208 MHz
Capacity from 32GBy to 2TBy



            ©Arasan Chip Systems Inc. 2011
SD 4.0 Controller Architecture




  ©Arasan Chip Systems Inc. 2011
Compliance

Current to SD 4.0 (rev. April 2011)
Only announced product in the market




             ©Arasan Chip Systems Inc. 2011
Deliverables

RMM (Reuse Methodology Manual)
compliant Verilog
Configurable Behavioral models
Verification Suite & Test Cases
Documentation and Design Support




            ©Arasan Chip Systems Inc. 2011
Total IP Solutions

      Features
           • Analog and Digital cores, with no gaskets or
             wrappers for efficient, low-gate design
           • Software, Synthesis scripts and Test
             Environments
           • Verification IP, ESL models
           • HW Development Kits & Verification Platforms
           • Design Services



                         ©Arasan Chip Systems Inc. 2011
December 21, 2011                                         Page 8
Total IP Solutions

        Benefits
         • Compliance across the standard
         • Single supplier – Single support
         • Guaranteed compatibility
         • Lowest overall cost and risk
         • Seamless integration from PHY to SW layers
         • Fastest cycle: MRD to SoC




                     ©Arasan Chip Systems Inc. 2011
December 21, 2011                                     Page 9

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SD 4.0 from Arasan Chip Systems

  • 1. Introducing SD 4.0 Device Controller By Dennis McCarty ©Arasan Chip Systems Inc. 2011
  • 2. Arasan Chip Systems Total IP Solutions SD 4.0 Improvements Core Architecture Deliverables Arasan Advantages ©Arasan Chip Systems Inc. 2011
  • 3. Arasan Total IP Solutions ©Arasan Chip Systems Inc. 2011
  • 4. SD 4.0 Background UHS-II PHY for faster throughput • 1.56 GB/s/lane at 52MHz • 300 MB/s overall Differential signaling • D0+/- and D1+/- Bus clock 208 MHz Capacity from 32GBy to 2TBy ©Arasan Chip Systems Inc. 2011
  • 5. SD 4.0 Controller Architecture ©Arasan Chip Systems Inc. 2011
  • 6. Compliance Current to SD 4.0 (rev. April 2011) Only announced product in the market ©Arasan Chip Systems Inc. 2011
  • 7. Deliverables RMM (Reuse Methodology Manual) compliant Verilog Configurable Behavioral models Verification Suite & Test Cases Documentation and Design Support ©Arasan Chip Systems Inc. 2011
  • 8. Total IP Solutions Features • Analog and Digital cores, with no gaskets or wrappers for efficient, low-gate design • Software, Synthesis scripts and Test Environments • Verification IP, ESL models • HW Development Kits & Verification Platforms • Design Services ©Arasan Chip Systems Inc. 2011 December 21, 2011 Page 8
  • 9. Total IP Solutions Benefits • Compliance across the standard • Single supplier – Single support • Guaranteed compatibility • Lowest overall cost and risk • Seamless integration from PHY to SW layers • Fastest cycle: MRD to SoC ©Arasan Chip Systems Inc. 2011 December 21, 2011 Page 9