This session includes a discussion on rapid prototyping concepts using Xilinx All Programmable FPGAs and SoCs with Analog Devices high speed and precision products. Covered in this session will be common use cases for Xilinx devices in DSP applications that interface to high speed analog. An overview will be provided of how Xilinx accelerates development with DSP platforms that can be used to quickly evaluate and prototype systems that include high speed analog, programmable logic, and embedded processing. Also covered will be an introduction to Xilinx’s new Vivado Design Suite development environment that shortens design cycles by providing an IP centric design flow, easy to use design analysis and debug, and high level design flows supporting C/C++ and MATLAB/Simulink.
2. The Signal Processing Design Challenge
Requires 4 distinct skill sets
Analog, Digital, Software, IO
Analog and Digital designs
need to be optimized together
to maximize system
performance and minimize
hardware cost
Requires real world data for
testing to insure functional
correctness
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3. Rapid Prototyping Addresses this Challenge by
Providing:
Analog Interfaces that can be easily programmed
Digital hardware that can be easily configured with
algorithms
MATLAB/Simulink
C/C++
Large ecosystem of interchangeable analog interfaces
FMC
PMODs
Partners working together!
Algorithms
Analog
Digital
Software
High-Speed IO
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4. Agenda
Xilinx All Programmable Devices for Signal Processing
Signal Processing System Design Considerations
Xilinx DSP Design Environment
DUC/DDC Design using Model Based Design
Xilinx JESD204B Solution
Rapid Prototyping using Xilinx DSP Platforms
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5. Agenda
Xilinx All Programmable Devices for Signal Processing
Signal Processing System Design Considerations
Xilinx DSP Design Environment
DUC/DDC Design using Model Based Design
Xilinx JESD204B Solution
Rapid Prototyping using Xilinx DSP Platforms
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6. Lowest Total Power
and System Cost
Industry’s Best
Price-Performance
Industry’s Highest
System Performance
and Capacity
Scalable Optimized 28 nm Architecture Enables
Design Portability
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Low-end HDTVHigh-end
2 Channel 4 Channel 8+ Channel
7. Lowest Total Power
and System Cost
Industry’s Best
Price-Performance
Industry’s Highest
System Performance
and Capacity
Scalable Optimized 28 nm Architecture Enables
Design Portability
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Low-end HDTVHigh-end
2 Channel 4 Channel 8+ Channel
11. Xilinx 7 Series Transceiver
7 series offers a full transceiver portfolio for variant customer needs
Ultra-high performance GTZ: 28.05Gb/s X 16
High-end Low-power GTH: 13.1Gb/s X 96
Mid-Range GTX: 12.5Gb/s X 32
High-Volume Low-Power GTP: 6.6Gb/s X 16
Virtex-7 HT has up to 2.802Tbps total transceiver bandwidth
16 GTZ and 72 GTH transceivers
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12. Jitter Performance
7 series transceivers offer the best jitter performance at 6Gb/s,
10Gb/s+ and 28Gb/s in FPGA industry
Both transmitter and receiver use the high performance PLL
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6.25Gb/s 10.3125Gb/s
28Gb/s13.1Gb/s
13. Agenda
Xilinx All Programmable Devices for Signal Processing
Signal Processing System Design Considerations
Xilinx DSP Design Environment
DUC/DDC Design using Model Based Design
Xilinx JESD204B Solution
Rapid Prototyping using Xilinx DSP Platforms
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14. Oversampling and Process Gain
For a Gaussian signal with signal power Ps and total noise power
due to quantization Pn the Signal to Noise Ration is
SNR = Ps / Pn
Oversampling by M improves the SNR
Pnb = Noise power in the signal
bandwidth (B)
M = Oversampling Factor
Pnb = Pn / M
Each 2X over-sampling improves the SNR by 3db
SNR = Ps / Pnb
SNR = M*Ps / P
Faster Sample Rates However leads to
More difficult timing closure in the FPGA design
Extra FPGA Resources
Higher Power Consumption
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Ps = Signal Power
Pn = Quantization Noise Power
B = Bandwidth of Interest
Nyquist = 2*B
Fs = Actual Sampling Rate
17. System Design Considerations
Higher analog IF Sample rates result in better SNR
Designing a digital down converter that minimizes hardware
resources
IF Sampling clock and the decimation filtering clocks need to be
multiples of each other
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DSP48
18. Improving Area Efficiency using Hardware
Overclocking
The DSP Resources in the FPGA can be overclocked to save
hardware resources
DSP48E1 slice Fmax = 741 MHz at 28nm
Implement more channels or more signal processing with smaller All
Programmable FPGAs or SoCs
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X
X
X
100 MHz
X
Time Division Mux Time Division DeMux
100 MHz 300 MHz 100 MHz
3X Over Clocking
DSP48
19. Agenda
Xilinx All Programmable Devices for Signal Processing
Signal Processing System Design Considerations
Xilinx DSP Design Environment
DUC/DDC Design using Model Based Design
Xilinx JESD204B Solution
Rapid Prototyping using Xilinx DSP Platforms
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20. DSP Design Methodology Leadership
Flexible design environment
Floating-point and Fixed-point
Hardware Generation
Real time analog data
acquisition
World class C design flow
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HDL
Coder
System
Generator
Vivado
HLS
ZC706
MATLAB / Simulink
Toolbox IP Xilinx IP
MATLAB
Simulink
MATLAB
Simulink
C/C++
C Libraries
Analog
Signals
A/D
D/A
Vivado
RTL
IP Catalog
Vivado System Edition
Algorithm Specification
AD9250
AD9129
21. DSP IP and Reference Designs Leadership
DSP IP libraries available for multiple design environments
Industries most advanced library of LTE specific wireless IP
Reference Designs provide working starting points
DSP, SDR, Wireless, Aerospace and Defense
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LTE Specific IP General Wireless IP Video IP HLS Libraries
LTE Turbo Enc/Dec Convolutional Encoder Scalar Math.h
LTE Channel Enc/Dec Viterbi Decoder Color Correction Floating Point library
LTE MIMO Enc/Dec DFT/iDFT Timing controller OpenCV
LTE FFT DUC/DDC Compiler On-Screen Display AXI Interfaces
LTE Channel Estimator FIR Compiler Image Edge Enhancement Linear Algebra *
LTE PUCCH Receiver DDS Compiler H.264 Encoder
LTE RACH Detector CORDIC Color Space Converter
RTL
MATLAB/
Simulink
C/C++
22. Xilinx System Generator for DSP
Enables MATLAB/Simulink for DSP FPGA Design
100+ Xilinx optimized DSP building blocks
Automatic code generation
Supports parameterization in MATLAB
Vivado Integration
Import C-based IP from Vivado HLS
Automatic bitstream generation
Vivado Project File generation
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System Generator for DSP
23. Vivado High-Level C/C++ Synthesis
Comprehensive coverage
C/C++/SystemC
Arbitrary precision
Floating-point
Accelerated verification
2 to 3 orders of magnitude
faster than RTL for larger
design
Fast compilation and design
exploration
Algorithm feasibility
Architecture Iteration
Customer proven results
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24. Introducing Vivado IP Integrator
IP Deployment and Assembly
Abstract IP Assembly
Does not require RTL
Debug integration
Intelligent IP Integration
Real time design rule checks
Parameter propagation
Designer Assistance
IP Aware AXI Interconnect
Automated interface
Device driver & address map generation
25. Use with High-Level Tool Flows and Design
Subsystems
IP
Catalog
IP Integrator
Vivado HLS
System Generator for DSP
Vivado Integrated Design Environment
Populate the Vivado
IP Catalog using High-
Level Design tools
• HLS
• System Generator
Integrate IP into
design subsystems
for Xilinx platforms
27. High-level Hardware Debugging
Flexible, targeted probing of
HDL and XDC using
MARK_DEBUG property
RTL and synthesized netlist
probing in multiple views
System-level probing inside
of IP integrator view
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entity FIR is
port (clk : in
rst : in
din : in
HDL
SchematicHierarchy
Debug Probe
Vivado IP
Integrator
28. Agenda
Xilinx All Programmable Devices for Signal Processing
Signal Processing System Design Considerations
Xilinx DSP Design Environment
DUC/DDC Design using Model Based Design
Xilinx JESD204B Solution
Rapid Prototyping using Xilinx DSP Platforms
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29. DUC/DDC Architectural Considerations
Both system performance and hardware resources should be taken
into account
Pulse shaping needs to be performed on TX / RX side
Wideband / Narrowband signal
Filter type and # of filter stages
IF Sampling rate vs Programmable Logic Fmax
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30. Using Model Based Design to Explore Filter
Configurations
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Anti-Aliasing
Filter
Filter Length
and Sample
Rate for 1st
Filter
Filter Length
and Sample
Rate for 2nd
Filter
Filter Length
and Sample
Rate for 3rd
Filter
Architecture
of choice
Configuration 1 91 taps (↑8)
61.44 MSPS
Configuration 2 47 taps (↑4)
30.72 MSPS
11 taps (↑2)
61.44 MSPS
Configuration 3 23 taps (↑4)
15.38 MSPS
25 taps (↑2)
61.44 MSPS
Configuration 4 23 taps (↑2)
15.38 MSPS
11 taps (↑2)
30.72 MSPS
11 taps (↑2)
61.44 MSPS
√
MathWorks FDATool
32. Correct by Construction Hardware Design
using System Generator
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System Generator
Hardware Design
Simulink
Executable Spec
Xilinx Gateways define FPGA Boundary
33. Improve Results through Overclocking
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Resource Separate Filter Chains TDM TDM + 3X Overclocking
DUC IF Sample Rate 61.44 MHz 61.44 MHz 61.44 MHz
Hardware Clock Frequency 61.44 MHz 122.88 MHz 368.64 MHz
LUTs 1486 952 961
Registers 1987 1230 1176
DSP48E1 27 17 11
DSP48E1s used in Filters 20 10 4
34. Agenda
Xilinx All Programmable Devices for Signal Processing
Signal Processing System Design Considerations
Xilinx DSP Design Environment
DUC/DDC Design using Model Based Design
Xilinx JESD204B Solution
Rapid Prototyping using Xilinx DSP Platforms
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35. Xilinx JESD204 IP v3.1 (Released in 2012.4)
Designed to JEDEC JESD204B
standard specification
Supports Transmit, Receive, and
Duplex (TX & RX) Modes
1 to 8 lane configurations up to
12.5 Gbps
Support for subclass 0, 1, and 2
Deterministic latency for
subclass 1 and 2
Supports GTX, GTH, GTP
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JESD204B
State
Machine
GT
TILE
Clocks
Management
Registers
Control &
Status
JESD204 Data (AXI4-Stream)
Test Data
Gen/
Checker
Status & Control
(AXI4-Lite)
36. Wizard Based JESD204 IP Core Generation
Easy to use Graphical Interface
Generated Files include
The netlist file for the core
XCO files
Release notes and documentation
A Verilog example design and
demonstration test bench
Scripts to synthesize, implement
and simulate the example design
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38. Analog Devices Scan Viewer
Displays Eye Scan diagram for
JESD204B transceivers
Leverages the eyescan block in
the Xilinx 7-series transceivers
Validate interface
Reusable into production designs
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39. Agenda
Xilinx All Programmable Devices for Signal Processing
Signal Processing System Design Considerations
Xilinx DSP Design Environment
DUC/DDC Design using Model Based Design
Xilinx JESD204B Solution
Rapid Prototyping using Xilinx DSP Platforms
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41. JESD204B High-Speed ADC Demo
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Analog Devices’
AD9250-FMC-
250EBZ 14-bit /
250 MSPS
4-ch ADC
AD9250 High
Speed
JESD204B
Serdes
Outputs Data
Eye @ 5Gbps
Analog Input
(Single-Tone FFT with
fIN = 90.1 MHz)
Ethernet data
connection to PC
for Verification of
Analog Signal on
VisualAnalog™
Xilinx Kintex-7 FPGA KC705 Eval Kit
Recovered Eye
(after EQ/CDR)
42. Summary
View Demonstrations at Show
Analog Devices Booth
JESD204B Platform Demonstration
Xilinx Booth
Zynq SDR Kit with ZC702
Development board
Artix-7 AMS Demo
Get Started Today with the Zynq
SDR Kit
Learn More at
www.xilinx.com/DSP
www.mathworks.com/Xilinx
www.mathworks.com/zynq
www.analog.com/xilinx
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