23. Block Diagram – 8 CPU Modules CPU Module H CPU Module G CPU Module F CPU Module E CPU Module D CPU Module C CPU Module B CPU Module A CPU0 CPU2 CPU1 CPU3 CPU4 CPU5 CPU6 CPU7 ILOM 8132 PCI-X Tunnel CK8-04 LSI SAS1064 SHARED 100 MHz bus FW82546 FW82546 PCI-X 100 MHz PCI-X 100 MHz PCI-E 8-lane PCI-E 8-lane PCI-E 4-lane Motorola MPC8248 SP Video over LAN Redirect VGA Video SAS HDDs 4 x 1 GB Ethernet DVI Video BCM 5221 Managed Power Supply Managed Power Supply Managed Power Supply Managed Power Supply Management Ethernet Serial Super I/O USB HUB IDE CD/DVD Rear USB Front USB USB [2..4] USB 1 USB 5 IDE USB 0 64 MB DDR SDRAM 32 MB FLASH IO-04 PCI-E 8-lane PCI-E 8-lane PCI-E 4-lane Rage XL All HT links - 1 GHz 8 GB/sec
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Editor's Notes
What is not included Hypertransport interconnect
Explain bus loading 10-12 loads. Explain use of PCI bridges to extend the number of devices PCI implements reflective wave switching signal drivers The driver drives a half signal swing signal on the rising edge of the PCI clock. The signal propogates down the PCI bus and is reflected at the end of the transmission line where there is no termination. The reflection causes the half signal to double. Half duplex. Show how the bus is half duplex – only one action can occur on the bus at a time, ie transmit or receive. These cannot occur at the same time
Take our 8 bit character 10101010 divide into a 3bit and 5 bit entry as below 101 01010 transpose the entry 01010 101 if data the entry becomes D 10.5 we then lookup the entry for D10 and these 5bits become a six bit paqtter We then lookup the entry for the .5 and these three bits become four bits ans adding the two together become 10bits D10 becomes 101010 .5 becomes 1010 10b = 1010101010 D31.7 (all 1s) becomes 101011. 1110/0111
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