Original N-CHANNEL MOSFET FDS4480 4480 40V SOP-8 New Fairchild
RSLogix 5000 Report(s)
1. MainRoutine - Ladder Diagram Page 1
PROJECT_REV:MainTask:MainProgram 01-Oct-13 1:27:43 PM
Total number of rungs in routine: 11 D:vtrockwellscadaPROJECT_REV.ACD
RSLogix 5000
0
START
OP
/
OL
/
STOP OP
1 /
PAUSE OP
/
T1.DN
EN
DN
Timer On Delay
Timer T1
Preset 1000
Accum 429
TON
2
T1.DN
CU
DN
Count Up
Counter C1
Preset 60
Accum 45
CTU
3 /
PAUSE
Limit Test (CIRC)
Low Limit 0
Test C1.ACC
45
High Limit 20
LIM
Limit Test (CIRC)
Low Limit 31
Test C1.ACC
45
High Limit 40
LIM
Limit Test (CIRC)
Low Limit 51
Test C1.ACC
45
High Limit 60
LIM
CONV_LAMP
4 /
PAUSE
Limit Test (CIRC)
Low Limit 21
Test C1.ACC
45
High Limit 29
LIM FILL_LAMP
2. MainRoutine - Ladder Diagram Page 2
PROJECT_REV:MainTask:MainProgram 01-Oct-13 1:27:44 PM
Total number of rungs in routine: 11 D:vtrockwellscadaPROJECT_REV.ACD
RSLogix 5000
5 /
PAUSE
Limit Test (CIRC)
Low Limit 41
Test C1.ACC
45
High Limit 45
LIM CAPPING_LAMP
6 Equal
Source A C1.ACC
45
Source B 60
EQU
RES
C1
7 Limit Test (CIRC)
Low Limit 0
Test C1.ACC
45
High Limit 20
LIM PHASE1
8 Limit Test (CIRC)
Low Limit 31
Test C1.ACC
45
High Limit 40
LIM PHASE2
9 Limit Test (CIRC)
Low Limit 45
Test C1.ACC
45
High Limit 60
LIM PHASE3
10
STOP
RES
C1
(End)